---------------------------------------------------------------------------------------------     File Name: MT48LC1M18A1.VHD--       Version: 0.0c--          Date: April 20th, 1999--         Model: Behavioral--     Simulator: Model Technology VLOG (PC version 5.2e PE)----  Dependencies: None----        Author: Son P. Huynh--         Email: sphuynh@micron.com--         Phone: (208) 368-3825--       Company: Micron Technology, Inc.--   Part Number: MT48LC1M16A1 (512k  x 16 x 2 Banks)----   Description: Micron 16Mb SDRAM----    Limitation: - Doesn't check for 4096-cycle refresh----          Note: - Set simulator resolution to "ps" accuracy----    Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --                WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.----                Copyright (c) 1998 Micron Semiconductor Products, Inc.--                All rights researved----  Rev   Author          Phone         Date        Changes--  ----  ----------------------------  ----------  ---------------------------------------  0.0c  Son P. Huynh    208-368-3825  04/20/1999  Fix precharge to different bank--        Micron Technology Inc.                      terminate current bank----  0.0b  Son P. Huynh    208-368-3825  12/09/1998  Fix some timing check problem--        Micron Technology Inc.                    - Improve model functionality----  0.0a  Son P. Huynh    208-368-3825  08/10/1998  First Release--        Micron Technology Inc.                    - Simple testbench included-----------------------------------------------------------------------------------------LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE WORK.mti_pkg.ALL;PACKAGE mt48lc1m16a1_PKG ISCOMPONENT mt48lc1m16a1      GENERIC (        tAC       : TIME    :=  6.0 ns;     -- Timing parameter for -10 device        tAH       : TIME    :=  1.0 ns;        tAS       : TIME    :=  3.0 ns;        tCH       : TIME    :=  3.5 ns;        tCL       : TIME    :=  3.5 ns;        tCK       : TIME    := 10.0 ns;        tDH       : TIME    :=  1.0 ns;        tDS       : TIME    :=  3.0 ns;        tCKH      : TIME    :=  1.0 ns;        tCKS      : TIME    :=  3.0 ns;        tCMH      : TIME    :=  1.0 ns;        tCMS      : TIME    :=  3.0 ns;        tOH       : TIME    :=  2.5 ns;        tHZ       : TIME    :=  6.0 ns;        tMRD      : INTEGER :=  2;--        tRAS      : TIME    := 60.0 ns;        tRAS      : TIME    := 48.0 ns;--        tRC       : TIME    := 90.0 ns;        tRC       : TIME    := 80.0 ns;--        tRCD      : TIME    := 30.0 ns;        tRCD      : TIME    := 24.0 ns;--        tRP       : TIME    := 30.0 ns;        tRP       : TIME    := 24.0 ns;--        tRRD      : TIME    := 20.0 ns;        tRRD      : TIME    := 16.0 ns;        tWR       : INTEGER :=  1;        addr_bits : INTEGER := 11;        data_bits : INTEGER := 16;        col_bits  : INTEGER :=  8    );    PORT (        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');        Ba    : IN    STD_LOGIC := '0';        Clk   : IN    STD_LOGIC := '0';        Cke   : IN    STD_LOGIC := '0';        Cs_n  : IN    STD_LOGIC := '1';        Ras_n : IN    STD_LOGIC := '0';        Cas_n : IN    STD_LOGIC := '0';        We_n  : IN    STD_LOGIC := '0';        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"    );END component;END mt48lc1m16a1_PKG;LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE WORK.mti_pkg.ALL;ENTITY mt48lc1m16a1 IS    GENERIC (        tAC       : TIME    :=  6.0 ns;     -- Timing parameter for -10 device        tAH       : TIME    :=  1.0 ns;        tAS       : TIME    :=  3.0 ns;        tCH       : TIME    :=  3.5 ns;        tCL       : TIME    :=  3.5 ns;        tCK       : TIME    := 10.0 ns;        tDH       : TIME    :=  1.0 ns;        tDS       : TIME    :=  3.0 ns;        tCKH      : TIME    :=  1.0 ns;        tCKS      : TIME    :=  3.0 ns;        tCMH      : TIME    :=  1.0 ns;        tCMS      : TIME    :=  3.0 ns;        tOH       : TIME    :=  2.5 ns;        tHZ       : TIME    :=  6.0 ns;        tMRD      : INTEGER :=  2;        tRAS      : TIME    := 60.0 ns;        tRC       : TIME    := 90.0 ns;        tRCD      : TIME    := 30.0 ns;        tRP       : TIME    := 30.0 ns;        tRRD      : TIME    := 20.0 ns;        tWR       : INTEGER :=  1;        addr_bits : INTEGER := 11;        data_bits : INTEGER := 16;        col_bits  : INTEGER :=  8    );    PORT (        Dq    : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');        Addr  : IN    STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');        Ba    : IN    STD_LOGIC := '0';        Clk   : IN    STD_LOGIC := '0';        Cke   : IN    STD_LOGIC := '0';        Cs_n  : IN    STD_LOGIC := '1';        Ras_n : IN    STD_LOGIC := '0';        Cas_n : IN    STD_LOGIC := '0';        We_n  : IN    STD_LOGIC := '0';        Dqm   : IN    STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"    );END mt48lc1m16a1;ARCHITECTURE behave OF mt48lc1m16a1 IS    TYPE   State       IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A);    TYPE   Array2xI    IS ARRAY (1 DOWNTO 0) OF INTEGER;    TYPE   Array2xB    IS ARRAY (1 DOWNTO 0) OF BIT;    TYPE   Array4xB    IS ARRAY (3 DOWNTO 0) OF BIT;    TYPE   Array2x2BV  IS ARRAY (1 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);    TYPE   Array4xCBV  IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);    TYPE   Array_state IS ARRAY (3 DOWNTO 0) OF State;    SIGNAL Operation : State := NOP;    SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');    SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';    SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';    SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';    SIGNAL Cas_latency_1, Cas_latency_2, Cas_latency_3 : BIT := '0';    SIGNAL Ras_in, Cas_in, We_in : BIT := '0';    SIGNAL Write_burst_mode : BIT := '0';    SIGNAL Sys_clk, CkeZ : BIT := '0';    -- Checking internal wires    SIGNAL Pre_chk : BIT_VECTOR (1 DOWNTO 0) := "00";    SIGNAL Act_chk : BIT_VECTOR (1 DOWNTO 0) := "00";    SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';    SIGNAL Bank_chk : BIT := '0';    SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');    SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');    BEGIN        -- CS# Decode        WITH Cs_n SELECT            Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',                      '1' WHEN '1',                      '1' WHEN OTHERS;        WITH Cs_n SELECT            Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',                      '1' WHEN '1',                      '1' WHEN OTHERS;        WITH Cs_n SELECT            We_in  <= TO_BIT (We_n,  '1') WHEN '0',                      '1' WHEN '1',                      '1' WHEN OTHERS;                -- Commands Decode        Active_enable   <= NOT(Ras_in) AND     Cas_in  AND     We_in;        Aref_enable     <= NOT(Ras_in) AND NOT(Cas_in) AND     We_in;        Burst_term      <=     Ras_in  AND     Cas_in  AND NOT(We_in);        Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);        Prech_enable    <= NOT(Ras_in) AND     Cas_in  AND NOT(We_in);        Read_enable     <=     Ras_in  AND NOT(Cas_in) AND     We_in;        Write_enable    <=     Ras_in  AND NOT(Cas_in) AND NOT(We_in);        -- Burst Length Decode        Burst_length_1  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));        Burst_length_2  <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND     Mode_reg(0);        Burst_length_4  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND NOT(Mode_reg(0));        Burst_length_8  <= NOT(Mode_reg(2)) AND     Mode_reg(1)  AND     Mode_reg(0);        -- CAS Latency Decode        Cas_latency_1   <= NOT(Mode_reg(6)) AND NOT(Mode_reg(5)) AND     Mode_reg(4);        Cas_latency_2   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND NOT(Mode_reg(4));        Cas_latency_3   <= NOT(Mode_reg(6)) AND     Mode_reg(5)  AND     Mode_reg(4);        -- Write Burst Mode        Write_burst_mode <= Mode_reg(9);        -- System Clock        int_clk : PROCESS (Clk)            begin                IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN                    CkeZ <= TO_BIT(Cke, '1');                END IF;                Sys_clk <= CkeZ AND TO_BIT(Clk, '0');        END PROCESS;        state_register : PROCESS            TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits - 1 DOWNTO 0);            TYPE ram_pntr IS ACCESS ram_type;            TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;            VARIABLE Bank0 : ram_stor;            VARIABLE Bank1 : ram_stor;            VARIABLE Row_index, Col_index : INTEGER := 0;            VARIABLE Dq_temp : BIT_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Col_addr : Array4xCBV;            VARIABLE Bank_addr : Array4xB;            VARIABLE Dqm_reg : Array2x2BV;            VARIABLE Bank, Previous_bank : BIT := '0';            VARIABLE B0_row_addr, B1_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Burst_counter : INTEGER := 0;            VARIABLE Command : Array_state;            VARIABLE A10_precharge, Bank_precharge : Array4xB;            VARIABLE Auto_precharge, Read_precharge, Write_precharge : Array2xB;            VARIABLE Count_precharge : Array2xI;            VARIABLE RW_interrupt_write : BIT := '0';            VARIABLE Data_in_enable, Data_out_enable : BIT := '0';            VARIABLE Pc_b0, Pc_b1 : BIT := '0';            VARIABLE Act_b0, Act_b1 : BIT := '0';            -- Timing Check