VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');            VARIABLE Burst_counter : INTEGER := 0;            VARIABLE Command : Array_state;            VARIABLE A10_precharge, Bank_precharge : Array4xB;            VARIABLE Auto_precharge, Read_precharge, Write_precharge : Array2xB;            VARIABLE Count_precharge : Array2xI;            VARIABLE RW_interrupt_write : BIT := '0';            VARIABLE Data_in_enable, Data_out_enable : BIT := '0';            VARIABLE Pc_b0, Pc_b1 : BIT := '0';            VARIABLE Act_b0, Act_b1 : BIT := '0';            -- Timing Check            VARIABLE MRD_chk : INTEGER := 0;            VARIABLE RC_chk, RRD_chk  : TIME    := 0 ns;            VARIABLE RAS_chk0, RAS_chk1 : TIME := 0 ns;            VARIABLE RCD_chk0, RCD_chk1 : TIME := 0 ns;            VARIABLE RP_chk, RP_chk0, RP_chk1 : TIME := 0 ns;            VARIABLE WR_chk : Array2xI := (0 & 0);            -- Initialize empty rows            PROCEDURE Init_mem (Bank : BIT; Row_index : INTEGER) IS                VARIABLE i, j : INTEGER := 0;                BEGIN                    IF Bank = '0' THEN                        IF Bank0 (Row_index) = NULL THEN                        -- Check to see if row empty                            Bank0 (Row_index) := NEW ram_type;                  -- Open new row for access                            FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP            -- Filled row with zeros                                FOR j IN (data_bits - 1) DOWNTO 0 LOOP                                    Bank0 (Row_index) (i) (j) := '0';                                END LOOP;                            END LOOP;                        END IF;                    ELSIF Bank = '1' THEN                        IF Bank1 (Row_index) = NULL THEN                            Bank1 (Row_index) := NEW ram_type;                            FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP                                FOR j IN (data_bits - 1) DOWNTO 0 LOOP                                    Bank1 (Row_index) (i) (j) := '0';                                END LOOP;                            END LOOP;                        END IF;                    END IF;                END;                            -- Burst Counter            PROCEDURE Burst_decode IS                VARIABLE Col_int : INTEGER := 0;                VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');                BEGIN                    -- Advance Burst Counter                    Burst_counter := Burst_counter + 1;                    -- Burst Type                    IF Mode_reg (3) = '0' THEN                        Col_int := TO_INTEGER(Col);                        Col_int := Col_int + 1;                        TO_BITVECTOR (Col_int, Col_temp);                    ELSIF Mode_reg (3) = '1' THEN                        TO_BITVECTOR (Burst_counter, Col_vec);                        Col_temp (2) := Col_vec (2) XOR Col_brst (2);                        Col_temp (1) := Col_vec (1) XOR Col_brst (1);                        Col_temp (0) := Col_vec (0) XOR Col_brst (0);                    END IF;                    -- Burst Length                    IF Burst_length_2 = '1' THEN                        Col (0) := Col_temp (0);                    ELSIF Burst_length_4 = '1' THEN                        Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);                    ELSIF Burst_length_8 = '1' THEN                        Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);                    ELSE                        Col := Col_temp;                    END IF;                    -- Burst Read Single Write                    IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN                        Data_in_enable := '0';                    END IF;                    -- Data counter                    IF Burst_length_1 = '1' THEN                        IF Burst_counter >= 1 THEN                            IF Data_in_enable = '1' THEN                                Data_in_enable := '0';                            ELSIF Data_out_enable = '1' THEN                                Data_out_enable := '0';                            END IF;                        END IF;                    ELSIF Burst_length_2 = '1' THEN                        IF Burst_counter >= 2 THEN                            IF Data_in_enable = '1' THEN                                Data_in_enable := '0';                            ELSIF Data_out_enable = '1' THEN                                Data_out_enable := '0';                            END IF;                        END IF;                    ELSIF Burst_length_4 = '1' THEN                        IF Burst_counter >= 4 THEN                            IF Data_in_enable = '1' THEN                                Data_in_enable := '0';                            ELSIF Data_out_enable = '1' THEN                                Data_out_enable := '0';                            END IF;                        END IF;                    ELSIF Burst_length_8 = '1' THEN                        IF Burst_counter >= 8 THEN                            IF Data_in_enable = '1' THEN                                Data_in_enable := '0';                            ELSIF Data_out_enable = '1' THEN                                Data_out_enable := '0';                            END IF;                        END IF;                    END IF;                END;            BEGIN                WAIT ON Sys_clk;                    IF Sys_clk = '1' THEN                        -- Internal Command Pipeline                        Command(0) := Command(1);                        Command(1) := Command(2);                        Command(2) := Command(3);                        Command(3) := NOP;                        Col_addr(0) := Col_addr(1);                        Col_addr(1) := Col_addr(2);                        Col_addr(2) := Col_addr(3);                        Col_addr(3) := (OTHERS => '0');                        Bank_addr(0) := Bank_addr(1);                        Bank_addr(1) := Bank_addr(2);                        Bank_addr(2) := Bank_addr(3);                        Bank_addr(3) := '0';                        Bank_precharge(0) := Bank_precharge(1);                        Bank_precharge(1) := Bank_precharge(2);                        Bank_precharge(2) := Bank_precharge(3);                        Bank_precharge(3) := '0';                        A10_precharge(0) := A10_precharge(1);                        A10_precharge(1) := A10_precharge(2);                        A10_precharge(2) := A10_precharge(3);                        A10_precharge(3) := '0';                        -- Operation Decode                        IF Active_enable = '1' THEN                            Operation <= ACT;                        ELSIF Aref_enable = '1' THEN                            Operation <= A_REF;                        ELSIF Burst_term = '1' THEN                            Operation <= BST;                        ELSIF Mode_reg_enable = '1' THEN                            Operation <= LMR;                        ELSIF Prech_enable = '1' THEN                            Operation <= PRECH;                        ELSIF Read_enable = '1' THEN                            IF Addr(10) = '0' THEN                                Operation <= READ;                            ELSE                                Operation <= READ_A;                            END IF;                        ELSIF Write_enable = '1' THEN                            IF Addr(10) = '0' THEN                                Operation <= WRITE;                            ELSE                                Operation <= WRITE_A;                            END IF;                        ELSE                            Operation <= NOP;                        END IF;                        -- Dqm pipeline for Read                        Dqm_reg(0) := Dqm_reg(1);                        Dqm_reg(1) := TO_BITVECTOR(Dqm);                        -- Read or Write with Auto Precharge Counter                        IF Auto_precharge (0) = '1' THEN                            Count_precharge (0) := Count_precharge (0) + 1;                        END IF;                        IF Auto_precharge (1) = '1' THEN                            Count_precharge (1) := Count_precharge (1) + 1;                        END IF;                        -- tMRD Counter                        MRD_chk := MRD_chk + 1;                        -- tWR Counter                        WR_chk(0) := WR_chk(0) + 1;                        WR_chk(1) := WR_chk(1) + 1;                        -- Auto Refresh                        IF Aref_enable = '1' THEN                            -- Auto Refresh to Auto Refresh                            ASSERT (NOW - RC_chk >= tRC)                                REPORT "tRC violation during Auto Refresh"                                SEVERITY WARNING;                            -- Precharge to Auto Refresh                            ASSERT (NOW - RP_chk >= tRP)                                REPORT "tRP violation during Auto Refresh"                                SEVERITY WARNING;                            -- Banks must be idle before Refresh                            IF Pc_b1 = '0' OR Pc_b0 = '0' THEN                                ASSERT (FALSE)                                    REPORT "All banks must be Precharge before Auto Refresh"                                    SEVERITY WARNING;                            END IF;                            -- Record current tRC time                            RC_chk := NOW;                        END IF;                        -- Load Mode Register                        IF Mode_reg_enable = '1' THEN                            Mode_reg <= TO_BITVECTOR (Addr);                            IF (Pc_b0 /= '1' OR Pc_b1 /= '1') THEN                                ASSERT (FALSE)                                    REPORT "All bank must be Precharge before Load Mode Register"                                    SEVERITY WARNING;                            END IF;                            -- REF to LMR                            ASSERT (RC_chk >= tRC)                                REPORT "tRC violation during Load Mode Register"                                SEVERITY WARNING;                            -- LMR to LMR                            ASSERT (MRD_chk >= tMRD)                                REPORT "tMRD violation during Load Mode Register"                                SEVERITY WARNING;                            -- Record current tMRD time                            MRD_chk := 0;                        END IF;                        -- Active Block (latch Bank and Row Address)                        IF Active_enable = '1' THEN                            IF Ba = '0' AND Pc_b0 = '1' THEN                                Act_b0 := '1';                                Pc_b0 := '0';                                B0_row_addr := TO_BITVECTOR (Addr);                                RCD_chk0 := NOW;                                RAS_chk0 := NOW;                                -- Precharge to Active Bank 0                                ASSERT (NOW - RP_chk0 >= tRP)