REPORT "tRP violation during Activate Bank 0"                                    SEVERITY WARNING;                            ELSIF Ba = '1' AND Pc_b1 = '1' THEN                                Act_b1 := '1';                                Pc_b1 := '0';                                B1_row_addr := TO_BITVECTOR (Addr);                                RCD_chk1 := NOW;                                RAS_chk1 := NOW;                                -- Precharge to Active Bank 1                                ASSERT (NOW - RP_chk1 >= tRP)                                    REPORT "tRP violation during Activate Bank 1"                                    SEVERITY WARNING;                            ELSIF Ba = '0' AND Pc_b0 = '0' THEN                                ASSERT (FALSE)                                    REPORT "Bank 0 is not Precharged"                                    SEVERITY WARNING;                            ELSIF Ba = '1' AND Pc_b1 = '0' THEN                                ASSERT (FALSE)                                    REPORT "Bank 1 is not Precharged"                                    SEVERITY WARNING;                            END IF;                            -- Active Bank A to Active Bank B                            IF (Previous_bank /= TO_BIT(Ba)) AND (NOW - RRD_chk < tRRD) THEN                                ASSERT (FALSE)                                    REPORT "tRRD violation during activate"                                    SEVERITY WARNING;                            END IF;                            -- LMR to ACT                            ASSERT (MRD_chk >= tMRD)                                REPORT "tMRD violation during Activate"                                SEVERITY WARNING;                            -- AutoRefresh to Activate                            ASSERT (NOW - RC_chk >= tRC)                                REPORT "tRC violation during Activate"                                SEVERITY WARNING;                            -- Record current Bank and RRD_chk                            Previous_bank := TO_BIT(Ba);                            RRD_chk := NOW;                        END IF;                                                -- Precharge Block                        IF Prech_enable = '1' THEN                            IF Addr(10) = '1' THEN                                Pc_b0 := '1';                                Pc_b1 := '1';                                Act_b0 := '0';                                Act_b1 := '0';                                RP_chk0 := NOW;                                RP_chk1 := NOW;                                -- Activate to Precharge all banks                                ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))                                    REPORT "tRAS violation during Precharge all banks"                                    SEVERITY WARNING;                                -- tWR violation check for Write                                IF ((WR_chk(0) < tWR) AND (WR_chk(1) < tWR)) THEN                                    ASSERT (FALSE)                                        REPORT "tWR violation during Precharge all banks"                                        SEVERITY WARNING;                                END IF;                            ELSIF Addr(10) = '0' THEN                                IF Ba = '0' THEN                                    Pc_b0 := '1';                                    Act_b0 := '0';                                    RP_chk0 := NOW;                                    -- Activate to Precharge bank 0                                    ASSERT (NOW - RAS_chk0 >= tRAS)                                        REPORT "tRAS violation during Precharge bank 0"                                        SEVERITY WARNING;                                ELSIF Ba = '1' THEN                                    Pc_b1 := '1';                                    Act_b1 := '0';                                    RP_chk1 := NOW;                                    -- Activate to Precharge bank 1                                    ASSERT (NOW - RAS_chk1 >= tRAS)                                        REPORT "tRAS violation during Precharge bank 1"                                        SEVERITY WARNING;                                END IF;                                -- tWR violation check for Write                                IF (WR_chk(TO_INTEGER(Ba)) < tWR) THEN                                    ASSERT (FALSE)                                        REPORT "tWR violation during Precharge"                                        SEVERITY WARNING;                                END IF;                            END IF;                            -- Terminate a Write Immediately (if same bank or all banks)                            IF (Data_in_enable = '1' AND (Bank = TO_BIT(Ba) OR Addr(10) = '1')) THEN                                Data_in_enable := '0';                            END IF;                            -- Precharge Command Pipeline for READ                            IF CAS_latency_3 = '1' THEN                                Command(2) := PRECH;                                Bank_precharge(2) := TO_BIT (Ba);                                A10_precharge(2) := TO_BIT (Addr(10));                            ELSIF CAS_latency_2 = '1' THEN                                Command(1) := PRECH;                                Bank_precharge(1) := TO_BIT (Ba);                                A10_precharge(1) := TO_BIT (Addr(10));                            ELSIF CAS_latency_1 = '1' THEN                                Command(0) := PRECH;                                Bank_precharge(0) := TO_BIT (Ba);                                A10_precharge(0) := TO_BIT (Addr(10));                            END IF;                            -- Record Precharge Bank and Current tRP time                            RP_chk := NOW;                        END IF;                                                -- Burst Terminate                        IF Burst_term = '1' THEN                            IF CAS_latency_3 = '1' THEN                                Command(2) := BST;                            ELSIF CAS_latency_2 = '1' THEN                                Command(1) := BST;                            ELSIF CAS_latency_1 = '1' THEN                                Command(0) := BST;                            END IF;                        END IF;                                                -- Read, Write, Column Latch                        IF Read_enable = '1' OR Write_enable = '1' THEN                            -- Check to see if bank is open (ACT) for Read or Write                            IF ((Ba = '0' AND Pc_b0 = '1') OR (Ba = '1' AND Pc_b1 = '1')) THEN                                ASSERT (FALSE)                                    REPORT "Cannot Read or Write - Bank is not Activated"                                    SEVERITY WARNING;                            END IF;                            -- Activate to Read or Write                            IF Ba = '0' THEN                                ASSERT (NOW - RCD_chk0 >= tRCD)                                    REPORT "tRCD violation during Read or Write to Bank 0"                                    SEVERITY WARNING;                            ELSIF Ba = '1' THEN                                ASSERT (NOW - RCD_chk1 >= tRCD)                                    REPORT "tRCD violation during Read or Write to Bank 1"                                    SEVERITY WARNING;                            END IF;                            -- Read Command                            IF Read_enable = '1' THEN                                -- Read Terminate a Write Immediately                                IF Data_in_enable = '1' THEN                                    Data_in_enable := '0';                                    RW_interrupt_write := '1';                                END IF;                                -- CAS Latency Pipeline                                IF Cas_latency_3 = '1' THEN                                    IF Addr(10) = '1' THEN                                        Command(2) := READ_A;                                    ELSE                                        Command(2) := READ;                                    END IF;                                    Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));                                    Bank_addr (2) := TO_BIT (Ba);                                ELSIF Cas_latency_2 = '1' THEN                                    IF Addr(10) = '1' THEN                                        Command(1) := READ_A;                                    ELSE                                        Command(1) := READ;                                    END IF;                                    Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));                                    Bank_addr (1) := TO_BIT (Ba);                                ELSIF Cas_latency_1 = '1' THEN                                    IF Addr(10) = '1' THEN                                        Command(0) := READ_A;                                    ELSE                                        Command(0) := READ;                                    END IF;                                    Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));                                    Bank_addr (0) := TO_BIT (Ba);                                END IF;                            -- Write Command                            ELSIF Write_enable = '1' THEN                                IF Addr(10) = '1' THEN                                    Command(0) := WRITE_A;                                ELSE                                    Command(0) := WRITE;                                END IF;                                Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));                                Bank_addr (0) := TO_BIT (Ba);                                IF Data_in_enable = '1' THEN                                    RW_interrupt_write := '1';                                END IF;                            END IF;                            -- Read or Write with Auto Precharge                            IF Addr(10) = '1' THEN                                Auto_precharge (TO_INTEGER(Ba)) := '1';                                Count_precharge (TO_INTEGER(Ba)) := 0;                                IF Read_enable = '1' THEN                                    Read_precharge (TO_INTEGER(Ba)) := '1';                                ELSIF Write_enable = '1' THEN                                    Write_precharge (TO_INTEGER(Ba)) := '1';                                END IF;                            END IF;                        END IF;                        -- Read with AutoPrecharge Calculation                        --      The device start internal precharge when:                        --          1.  BL/2 cycles after command                        --      and 2.  Meet tRAS requirement                        --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)                        IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN                            IF (((NOW - RAS_chk0 >= tRAS) AND                                ((Burst_length_1 = '1' AND Count_precharge(0) >= 1)  OR                                 (Burst_length_2 = '1' AND Count_precharge(0) >= 2)  OR                                 (Burst_length_4 = '1' AND Count_precharge(0) >= 4)  OR                                 (Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR                                ((Read_enable = '1' OR Write_enable = '1') AND Count_precharge(0) >= 1)) THEN                                Pc_b0 := '1';                                Act_b0 := '0';                                RP_chk0 := NOW;                                Auto_precharge(0) := '0';                                Read_precharge(0) := '0';                                Write_precharge(0) := '0';                            END IF;                        END IF;                        IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN                            IF (((NOW - RAS_chk1 >= tRAS) AND                                ((Burst_length_1 = '1' AND Count_precharge(1) >= 1)  OR                                 (Burst_length_2 = '1' AND Count_precharge(1) >= 2)  OR                                 (Burst_length_4 = '1' AND Count_precharge(1) >= 4)  OR                                 (Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR                                ((Read_enable = '1' OR Write_enable = '1') AND Count_precharge(1) >= 1)) THEN                                Pc_b1 := '1';                                Act_b1 := '0';                                RP_chk1 := NOW;                                Auto_precharge(1) := '0';                                Read_precharge(1) := '0';                                Write_precharge(1) := '0';                            END IF;                        END IF;                                                -- Write with AutoPrecharge Calculation                        --      The device start internal precharge when:                        --          1.  tWR cycles after command                        --      and 2.  Meet tRAS requirement                        --       or 3.  Interrupt by a Read or Write (with or without Auto Precharge)                        IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN                            IF (((NOW - RAS_chk0 >= tRAS) AND                               (((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1)  OR                                 (Burst_length_2 = '1'                             AND Count_precharge(0) >= 2)  OR                                 (Burst_length_4 = '1'                             AND Count_precharge(0) >= 4)  OR                                 (Burst_length_8 = '1'                             AND Count_precharge(0) >= 8))) OR                                 (RW_interrupt_write = '1' AND WR_chk(0) >= 1)) THEN                                Pc_b0 := '1';