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Design Description: The SDRAM controller is designed for a Virtex device.
It's simulated with Micron SDRAM models. The design is verified with 
backannotated simulation at 125MHz. For a full functional description see 
Application Note 134:	http://www.xilinx.com/xapp/xapp134.pdf

Design Type: ISE (chip Virtex V300bg432-6)
	
Design Hierarchy:

sdrm			(top level)
 sdrm_tb.vhd	(Test Bench)
  sys_int		(system interface)
  sdrm_t		(SDRAM controller)
    sdrmc_state 	(state machine)
    brst_cntr 		(burst counter)
    rcd_cntr 		(ras-cas-delay counter)
    ref_cntr 		(refresh counter)
    cslt_cntr 		(cas-latency counter)
    ki_cntr		(keep-idle-during-refresh-active counter)

Simulation:
Requires the following simulation libraries:
	Unisims
	Simprims

The initial timing violations can be safely ignored. They are caused while the ram is
being initialized.


Warning: The File->Save Project As... operation of Project Navigator does not copy 
	files Which are not actual project or source files.  If this example is saved to a new 
	location, the user should manually copy the following files to the new location.

	For synthesis: 	
	For Simulation:	micron folder, wave_functional.do, and wave_timing.do files.


Design  Notes:

- NOTE: Simplicity users still need to remove use std.textio.all in all vhd files

- DLL:  (in sdrm module)
  . dll0: use for clock mirror, provide the clock for the external SDRAM
  . dll1: use for deskewing clock signal inside the FPGA (Clk_j), also provide clk2x (Clk_i)

- Use global clock buffers for clock signals:
  .  There are 4 BUFGPs in Virtex.  They provide low-skew high-fanout routings.

- Use LUT Shift Register to delay signals by certain number of clock cycles

  . delay DLL lock signal (in sdrm_t module)
  . delay data (in sys_int module) 

- Registering all inputs and ouputs to SDRAM: (in sdrm module)
  . All signals going to the SDRAM are registered in the IOB 
    This makes it easy to calculate timings b/t the FPGA and SDRAM
    For write cycles, add FPGA Tiockp to SDRAM Tsu
    For read cycles, add SDRAM Tac to FPGA Tsu and
  . The tristate signal for the data lines are also registered in the IOB 
  . Instead of 1 tristate signal for the Data lines, 
    we duplicate it to 4 signals, each having 8 loads.  
    This was done to reduce net delays on that tristate signal.  
    The tristate signal is sd_doe_n in sdrm 

- Use fast output buffers: (in sdrm module)
  . IOBUF_F_12: all signals interfacing to SDRAM
  These may create more bounce but are ~2ns faster than regular OBUFs	

- Use NODELAY mode for input buffers: (in ucf constraint file)
  . The default IBUF has additional delay to give negative hold time.  This 
    eliminates pad-to-pad hold time
  . Set NODELAY attribute on inputs to reduce IBUF delay by about 1.5ns

- Set timing constraints for place & route tool: (in ucf constraint file)
   . set clock period on input clock (Clkp)
   . set periods b/t clk1x and clk2x (Clk_j, Clk_i)
   . set OFFSET constraint for inputs and outputs 

Frequently asked questions:

1. Is RAS to CAS delay programmable?
  . No, the data registers has a fixed number of pipeline stages.  This 
    reference design supports RAS-to-CAS delay of 2 clock cycles.  If you 
    need to adjust to a different RAS-to-CAS delay, change the SRL16 Address 
    values in sys_int.v.  The address value should be (Trcd/Tck) +1
  . Note, you still need to write the RAS-to-CAS value to the Controller's 
    Mode Reg during PRECHARGE command.  The value should be (Trcd/Tck) -2

2. How do I modify the design to support 128Mb/256Mb SDRAM parts with a 64-bit data bus?
  . You'll need to add more IO buffers for the extra data and address signals (in sdrm.v) 
  . You'll need to change ADDR_MSB and DATA_MSB (in define.v) 
  . In the current design, instead of 1 tristate signal for the Data lines, 
    we duplicate it to 4 signals, each having 8 loads.  
    This was done to reduce net delays on that tristate signal.  
    You may need to add 4 more tristate lines if you're going to 64-bit.  
    The tristate signal is sd_doe_n in sdrm.v 


NOTE: If you are trying to run this example in a read-only location,    
the design hierachy will not display properly. Please copy the example  
project to a new location by using either Project Save As... from the File menu
pulldown in ISE or some other method of your choice. Copy the example to a location
where you have write permissions and the hiearchy will display properly. 


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