--core_design
--test_banch
--all right reserved

library ieee;
use ieee.std_logic_1164.all;

entity test is
  port(clk:out std_logic;
       reset:out std_logic;
       over_flow:out std_logic;
       data:out std_logic_vector(31 downto 0)
      );
end test;

architecture e of test is
component CPU 
  port(clk:in std_logic;
       reset:in std_logic;--high
       over_flow:out std_logic;
       data_ex:std_logic_vector(31 downto 0)
      );
end component;
constant high:std_logic:='1';
constant clk_delay:time:=20 ns;

signal data_sig:std_logic_vector(31 downto 0);
signal clk_sig:std_logic:='1';
signal reset_sig:std_logic;
signal over_flow_sig:std_logic;

begin
U1:CPU port map (clk_sig,reset_sig,over_flow_sig,data_sig);
data_sig<="11111101010101010101010101010101","10101010101010101010101010111111" after 80 ns;
data<=data_sig;
clk_sig<=not clk_sig after (clk_delay/2);
clk<=clk_sig;
reset_sig<='1','0' after 15 ns;
reset<=reset_sig;
over_flow<=over_flow_sig;
end e;