--core_design
--mux4_1
--all right reserved

library ieee;
use ieee.std_logic_1164.all;

entity mux4_1 is
  port (en:in std_logic_vector(1 downto 0);
  	in1:in std_logic_vector(31 downto 0);
  	in2:in std_logic_vector(31 downto 0);
  	in3:in std_logic_vector(31 downto 0);
  	in4:in std_logic_vector(31 downto 0);
  	out1:out std_logic_vector(31 downto 0)
       );
end mux4_1;

architecture b of mux4_1 is
begin
process(en,in1,in2,in3,in4)
begin
case en is
when "00" =>out1<=in1;
when "01" =>out1<=in2;
when "10" =>out1<=in3;
when "11" =>out1<=in4;
when others =>null;
end case;
end process;
end b;