library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned."+";

entity opt is
  port (reset:in std_logic;
    	in1:in std_logic_vector(15 downto 0);
  	in2:in std_Logic_vector(31 downto 0);
  	out1:out std_Logic_vector(31 downto 0);
  	out2:out std_Logic_vector(31 downto 0)
       );
end opt;

architecture d of opt is
function shift2 (a:std_logic_vector(31 downto 0)) return std_logic_vector is
variable b:std_logic_vector(31 downto 0);
begin
  b:=(others=>'0');
  for i in 15 downto 0 loop
   b(i+2):=a(i);
  end loop;
  return b;
end shift2;

begin
process(in1,in2,reset)
variable in1v:std_Logic_vector(31 downto 0);
variable in2v:std_Logic_vector(31 downto 0);
begin
 if reset='1' then
 out1<=(others=>'0');
 out2<=(others=>'0');
 elsif reset='0' then
 in1v(15 downto 0):=in1(15 downto 0);
 in1v(31 downto 16):=(others=>'0');
 out1<=in1v;
 in2v:=shift2(in1v);
 out2<=(in2 + in2v);
end if;
end process;
end d;