@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <24> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <25> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <26> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <27> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <28> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <29> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <30> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":198:0:198:1|Bit <31> of input in4 of instance U7 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <0> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <1> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <2> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <3> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <4> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <5> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <6> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <7> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <8> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <9> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <10> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <11> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <12> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <13> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <14> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <15> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <16> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <17> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <18> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <19> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <20> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <21> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <22> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <23> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <24> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <25> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <26> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <27> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <28> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <29> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <30> of input in4 of instance U4 is floating
@W:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":196:0:196:1|Bit <31> of input in4 of instance U4 is floating
@N:"D:\MY DOCUMENTS\New Folder (4)\coreofCPU.vhd":239:6:239:14|Found RAM ram_array, depth=32, width=32
@END
Process took 0.621 seconds realtime, 0.721 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.2, Build 175R, built Oct 24 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved


Automatic dissolve at startup in view:work.cpu(core) of U11(mux2_1)
Automatic dissolve at startup in view:work.cpu(core) of U10(dram)
Automatic dissolve at startup in view:work.cpu(core) of U9(mux2_1)
Automatic dissolve at startup in view:work.cpu(core) of U8(mux4_1)
Automatic dissolve at startup in view:work.cpu(core) of U7(mux4_1)
Automatic dissolve at startup in view:work.cpu(core) of U5(opt)
Automatic dissolve at startup in view:work.cpu(core) of U4(mux4_1_U4)
@N:"d:\my documents\new folder (4)\ins_rom.vhd":97:31:97:38|Generating ROM readdata_4[31:24]
@N:"d:\my documents\new folder (4)\ins_rom.vhd":95:30:95:37|Generating ROM readdata_4[15:8]
@N:"d:\my documents\new folder (4)\ins_rom.vhd":96:31:96:38|Generating ROM readdata_4[23:16]
@N:"d:\my documents\new folder (4)\ins_rom.vhd":94:29:94:34|Generating ROM readdata_4[7:0]
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[22] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[21] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[20] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[19] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[18] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[17] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[16] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[31] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[30] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[29] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[28] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[27] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[26] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[25] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[24] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":208:5:208:6|Removing sequential instance pc_out[23] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[31] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[30] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[29] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[28] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[27] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[26] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[25] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[24] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[23] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[22] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[21] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[20] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[19] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[18] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[17] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[16] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[15] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[14] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[13] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[12] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[11] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[10] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":224:10:224:11|Removing sequential instance ifid_out.iword[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 
Removed	FDR	idex_out.after_sign[31]
@W:"d:\my documents\new folder (4)\coreofcpu.vhd":260:6:260:7|Removing sequential instance idex_out.after_sign[31] of view:UNILIB.FDR(PRIM) because there are no references to its outputs 

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk

Net buffering Report for view:work.cpu(core):
pin:Q inst:ifid_out.pc[25] of UNILIB.FDR(PRIM) - loads: 132, segments 2, replicating source
pin:Q inst:ifid_out.pc[23] of UNILIB.FDR(PRIM) - loads: 132, segments 2, replicating source
pin:Q inst:ifid_out.pc[24] of UNILIB.FDR(PRIM) - loads: 259, segments 3, replicating source
pin:Q inst:ifid_out.pc[21] of UNILIB.FDR(PRIM) - loads: 164, segments 2, replicating source
pin:Q inst:ifid_out.pc[22] of UNILIB.FDR(PRIM) - loads: 133, segments 2, replicating source
reset_c - loads: 357, segments 5, buffering source
Added 5 Buffers
Added 6 Registers via replication
Added 0 LUTs via replication

@N:"d:\my documents\new folder (4)\coreofcpu.vhd":191:0:191:1|The module U1 is too small to be pipelined.
@N:"d:\my documents\new folder (4)\coreofcpu.vhd":14:7:14:15|Changing pad type from OBUF to OBUF_F_24 for pad over_flow_obuf to improve timing. 
@N|Automatic conversion of slower pads to faster pads can be turned off using attribute xc_fast_auto 
Timing driven replication report
pin:O inst:U2.shiftcnt_3[4] of VIRTEX.LUT3(PRIM) - loads: 54, segments: 2, replicating source
pin:O inst:U11.out1[1] of VIRTEX.LUT3(PRIM) - loads: 36, segments: 2, replicating source
pin:O inst:U11.out1[0] of VIRTEX.LUT3(PRIM) - loads: 36, segments: 2, replicating source
pin:O inst:U11.out1[2] of VIRTEX.LUT3(PRIM) - loads: 36, segments: 2, replicating source
pin:O inst:U2.shiftcnt_3[3] of VIRTEX.LUT3(PRIM) - loads: 59, segments: 2, replicating source
pin:O inst:U11.out1[3] of VIRTEX.LUT3(PRIM) - loads: 36, segments: 2, replicating source
pin:Q inst:idex_out.ex[6] of UNILIB.FDR(PRIM) - loads: 64, segments: 2, replicating source
pin:O inst:G_10502 of VIRTEX.LUT2(PRIM) - loads: 64, segments: 2, replicating source
pin:O inst:U2.shiftcnt_3_fast[4] of VIRTEX.LUT3(PRIM) - loads: 44, segments: 4, replicating source
pin:Q inst:memwb_out.wb[0] of UNILIB.FDR(PRIM) - loads: 39, segments: 3, replicating source
pin:O inst:U11.out1[1] of VIRTEX.LUT3(PRIM) - loads: 25, segments: 2, replicating source
pin:O inst:U11.out1[0] of VIRTEX.LUT3(PRIM) - loads: 25, segments: 2, replicating source
pin:O inst:U11.out1[2] of VIRTEX.LUT3(PRIM) - loads: 25, segments: 2, replicating source
pin:O inst:U11.out1[3] of VIRTEX.LUT3(PRIM) - loads: 25, segments: 2, replicating source
pin:O inst:U2.shiftcnt_3_fast[3] of VIRTEX.LUT3(PRIM) - loads: 31, segments: 3, replicating source
Added 3 Registers via timing driven replication
Added 16 LUTs via timing driven replication

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base D:\My Documents\New Folder (4)\rev_1\coreofCPU.srm
Writing EDIF Netlist and constraint files
Found clock cpu|clk with period 14.29ns 


##### START TIMING REPORT #####
# Timing Report written on Thu Jun 26 17:26:55 2003
#


Top view:              cpu
Paths requested:       5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.



Performance Summary