{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd 2 1 " "Found 2 design units and 1 entities in source file D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sdram64m16-behav " "Found design unit 1: sdram64m16-behav" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "sdram64m16-behav" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sdram64m16 " "Found entity 1: sdram64m16" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "sdram64m16" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 4 -1 0 } }  } 0}  } {  } 0 }
{  "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp3_s0_401u\[3\] data_in GND " "Reduced register temp3_s0_401u\[3\] with stuck data_in port to stuck value GND" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } }  } 0 }
{  "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp3_s0_401u\[1\] data_in GND " "Reduced register temp3_s0_401u\[1\] with stuck data_in port to stuck value GND" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } }  } 0 }
{  "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "temp2_s0_401u\[3\] data_in GND " "Reduced register temp2_s0_401u\[3\] with stuck data_in port to stuck value GND" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } }  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\lpm_counter.tdf 1 1 " "Found 1 design units and 1 entities in source file D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Found entity 1: lpm_counter" {  } { { "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\lpm_counter.tdf" "lpm_counter" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\lpm_counter.tdf" 212 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\alt_counter_stratix.tdf 1 1 " "Found 1 design units and 1 entities in source file D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Found entity 1: alt_counter_stratix" {  } { { "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "D:\\w2000_apply\\altera\\quatus2\\libraries\\megafunctions\\alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0 }
{  "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Registers with preset signals will power up high" {  } { { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 13 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 14 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 15 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 16 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 20 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 21 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 291 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 265 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } } { "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" "" "" { Text "D:\\all_work\\standard\\sdram4m16_L2_42\\sdram64m16.vhd" 86 -1 0 } }  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "203 " "Implemented 203 device resources" { { "Info" "ISCL_SCL_TM_IPINS" "30 " "Implemented 30 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Implemented 17 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "156 " "Implemented 156 logic cells" {  } {  } 0}  } {  } 0 }
{  "Info" "IMPP_MPP_USER_DEVICE" "sdram64m16 EP1C6Q240C8 " "Selected device EP1C6Q240C8 for design sdram64m16" {  } {  } 0 }
{  "Info" "IFITCC_FITCC_SIGNALPROBE_SMART_COMPILATION_OFF" "" "Smart compilation specified to OFF -- SignalProbe information will not be saved" {  } {  } 0 }