|sdram64m16
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[9].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[8].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[7].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[6].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[5].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[4].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[3].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[2].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[1].CLK
clkmain1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[0].CLK
clkmain1 => |sdram64m16|sdramclk
clkmain1 => ready_p1_402d~reg0.CLK
clkmain1 => cs_p1_402d~reg0.CLK
clkmain1 => ras_p1_402d~reg0.CLK
clkmain1 => cas_p1_402d~reg0.CLK
clkmain1 => addr_p3_402d[7]~reg0.CLK
clkmain1 => addr_p3_402d[6]~reg0.CLK
clkmain1 => addr_p3_402d[5]~reg0.CLK
clkmain1 => addr_p3_402d[4]~reg0.CLK
clkmain1 => addr_p3_402d[3]~reg0.CLK
clkmain1 => addr_p3_402d[2]~reg0.CLK
clkmain1 => addr_p3_402d[1]~reg0.CLK
clkmain1 => addr_p3_402d[0]~reg0.CLK
clkmain1 => a8_p0_402d~reg0.CLK
clkmain1 => ba_p3_402d~reg0.CLK
clkmain1 => we_p1_402d~reg0.CLK
clkmain1 => dqm_p3_402d~reg0.CLK
clkmain1 => temp_s0_402d[1].CLK
clkmain1 => temp_s0_402d[0].CLK
clkmain1 => temp0_s0_401u[2].CLK
clkmain1 => temp0_s0_401u[1].CLK
clkmain1 => temp0_s0_401u[3].CLK
clkmain1 => temp0_s0_401u[0].CLK
clkmain1 => length_s0_402d[0].CLK
clkmain1 => length_s0_402d[1].CLK
clkmain1 => length_s0_402d[2].CLK
clkmain1 => length_s0_402d[3].CLK
clkmain1 => length_s0_402d[4].CLK
clkmain1 => length_s0_402d[5].CLK
clkmain1 => length_s0_402d[6].CLK
clkmain1 => length_s0_402d[7].CLK
clkmain1 => refreshask_s1_404u.CLK
clkmain1 => temp1_s0_401u[1].CLK
clkmain1 => temp1_s0_401u[3].CLK
clkmain1 => temp1_s0_401u[0].CLK
clkmain1 => temp1_s0_401u[2].CLK
clkmain1 => refreshack_s1_402d.CLK
clkmain1 => temp2_s0_401u[1].CLK
clkmain1 => temp2_s0_401u[0].CLK
clkmain1 => temp2_s0_401u[2].CLK
clkmain1 => temp3_s0_401u[0].CLK
clkmain1 => temp3_s0_401u[2].CLK
xlength_3[7] => LessThan_469~95.DATAA
xlength_3[7] => i~17489.DATAA
xlength_3[6] => LessThan_469~116.DATAA
xlength_3[5] => LessThan_469~111.DATAA
xlength_3[4] => LessThan_469~109.DATAA
xlength_3[3] => LessThan_469~104.DATAA
xlength_3[2] => LessThan_469~102.DATAA
xlength_3[1] => LessThan_469~97.DATAA
xlength_3[0] => LessThan_469~97.DATAB
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[9].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[8].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[7].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[6].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[5].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[4].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[3].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[2].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[1].ACLR
reset_1 => lpm_counter:temp_s0_403d_rtl_0|alt_counter_stratix:wysi_counter|counter_cell[0].ACLR
reset_1 => ready_p1_402d~reg0.ACLR
reset_1 => cs_p1_402d~reg0.ACLR
reset_1 => ras_p1_402d~reg0.ACLR
reset_1 => cas_p1_402d~reg0.ACLR
reset_1 => a8_p0_402d~reg0.ACLR
reset_1 => we_p1_402d~reg0.ACLR
reset_1 => dqm_p3_402d~reg0.ACLR
reset_1 => temp_s0_402d[1].ACLR
reset_1 => temp_s0_402d[0].ACLR
reset_1 => temp0_s0_401u[0].ACLR
reset_1 => temp0_s0_401u[1].ACLR
reset_1 => temp0_s0_401u[3].ACLR
reset_1 => temp0_s0_401u[2].ACLR
reset_1 => addr_p3_402d[7]~4.DATAA
reset_1 => refreshask_s1_404u.ACLR
reset_1 => temp1_s0_401u[1].ACLR
reset_1 => temp1_s0_401u[3].ACLR
reset_1 => temp1_s0_401u[0].ACLR
reset_1 => temp1_s0_401u[2].ACLR
reset_1 => addr_p3_402d[7]~64.DATAA
reset_1 => refreshack_s1_402d.ACLR
reset_1 => temp2_s0_401u[1].ACLR
reset_1 => temp2_s0_401u[0].ACLR
reset_1 => temp2_s0_401u[2].ACLR
reset_1 => temp3_s0_401u[0].ACLR
reset_1 => temp3_s0_401u[2].ACLR
xrasaddr_3[7] => i~5383.DATAA
xcasaddr_3[7] => i~5383.DATAC
xrasaddr_3[6] => i~5487.DATAA
xcasaddr_3[6] => i~5487.DATAC
xrasaddr_3[5] => i~17605.DATAB
xcasaddr_3[5] => i~5505.DATAB
xrasaddr_3[4] => i~5610.DATAA
xcasaddr_3[4] => i~5610.DATAC
xrasaddr_3[3] => i~5714.DATAA
xcasaddr_3[3] => i~5714.DATAC
xrasaddr_3[2] => i~17616.DATAB
xcasaddr_3[2] => i~5732.DATAB
xrasaddr_3[1] => i~17627.DATAB
xcasaddr_3[1] => i~5751.DATAB
xrasaddr_3[0] => i~17638.DATAB
xcasaddr_3[0] => i~5770.DATAB
xrasaddr_3[8] => i~5811.DATAB
xrasaddr_3[9] => i~5976.DATAC
xwrite_1 => temp0_s0_401u[1].DATAC
xwrite_1 => temp0_s0_401u[2].DATAA
xwrite_1 => temp1_s0_401u[1].DATAD
xwrite_1 => temp1_s0_401u[0].DATAD
xwrite_1 => temp1_s0_401u[2].DATAC
xwrite_1 => temp2_s0_401u[1].DATAA
xwrite_1 => temp2_s0_401u[2].DATAB
xwrite_1 => i~3450.DATAB
xread_1 => temp0_s0_401u[1].DATAD
xread_1 => i~17482.DATAA
xread_1 => temp1_s0_401u[3].DATAB
xread_1 => temp2_s0_401u[1].DATAB
xread_1 => temp2_s0_401u[0].DATAC
sdramclk <= |sdram64m16|clkmain1
ready_p1_402d <= ready_p1_402d~reg0
cs_p1_402d <= cs_p1_402d~reg0
ras_p1_402d <= ras_p1_402d~reg0
cas_p1_402d <= cas_p1_402d~reg0
addr_p3_402d[7] <= addr_p3_402d[7]~reg0
addr_p3_402d[6] <= addr_p3_402d[6]~reg0
addr_p3_402d[5] <= addr_p3_402d[5]~reg0
addr_p3_402d[4] <= addr_p3_402d[4]~reg0
addr_p3_402d[3] <= addr_p3_402d[3]~reg0
addr_p3_402d[2] <= addr_p3_402d[2]~reg0
addr_p3_402d[1] <= addr_p3_402d[1]~reg0
addr_p3_402d[0] <= addr_p3_402d[0]~reg0
a8_p0_402d <= a8_p0_402d~reg0
ba_p3_402d <= ba_p3_402d~reg0
we_p1_402d <= we_p1_402d~reg0
dqm_p3_402d <= dqm_p3_402d~reg0