---chen wei cheng----91/01/26------
---riscpu3------------------
---modify from AHDL CODE---
LIBRARY ieee;                        
USE ieee.std_logic_1164.all;          
USE ieee.std_logic_arith.all;        
USE ieee.std_logic_unsigned.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
LIBRARY altera;
USE altera.MAXPLUS2.ALL;

ENTITY risccpu3 IS
      PORT
         (  --rqbb       :out std_logic_vector(7 downto 0);
            sysrest	   :   in std_logic; 
            sysclk     :   IN STD_LOGIC;
            iopt0        :   inout  std_logic_vector(7 downto 0);
            iopt1        :   inout  std_logic_vector(7 downto 0);
            iopt2        :   inout  std_logic_vector(7 downto 0);
            iopt3        :   inout  std_logic_vector(7 downto 0);
            tst          : out   std_logic
         );
end risccpu3;
            
ARCHITECTURE a OF risccpu3 IS	
TYPE reg16_8 IS ARRAY (15 DOWNTO 0) OF STD_LOGIC_VECTOR(7 downto 0);
TYPE reg4_12 IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(11 downto 0);

	
signal	cntp	: std_logic_vector(1 downto 0);
signal  t       : std_logic_vector(3 downto 0);

signal temp_muxa,temp_muxb : std_logic_2d(15 downto 0,7 downto 0);
SIGNAL rgg      : reg16_8;
SIGNAL stk      : reg4_12;
signal sp       :std_logic_vector(1 downto 0);



signal muxa_result : std_logic_vector(7 downto 0);
signal muxb_result : std_logic_vector(7 downto 0);

signal rqab     : std_logic_vector(7 downto 0);
signal rqbb     : std_logic_vector(7 downto 0);

signal pdx     : std_logic_vector(15 downto 0);
signal pdy     : std_logic_vector(15 downto 0);
signal pd      : std_logic_vector(15 downto 0);--- ROM output ------

signal aldb		:std_logic;
signal weny     :std_logic;
signal ws       :std_logic_vector(3 downto 0);
--SIGNAL ws         :INTEGER RANGE 0 TO 15;

signal rdi      :std_logic_vector(7 downto 0);

signal alo      :std_logic_vector(8 downto 0);
signal alox	    :std_logic_vector(8 downto 0);

signal rzr      :std_logic;
signal tcnd     : std_logic;
signal pushst   : std_logic;
signal pcadmx   :std_logic;
signal wen      :std_logic;
signal swen		:std_logic;
-----------------------------------------------
--      PC counter and operation            ---
-----------------------------------------------
signal pc			 : std_logic_vector(11 downto 0);
signal muxstk_result : std_logic_vector(11 downto 0);--- stack output---
signal pcadd_datab : std_logic_vector(11 downto 0);--- ---
signal pcadd_result : std_logic_vector(11 downto 0);
signal pcmx		 : std_logic;-- RETURN INS flag ---------
----------------------------------------------------------
signal tmp_pdx : std_logic_vector(2 downto 0);--- ---
signal tmp2 : std_logic_vector(2 downto 0);--- ---
signal tmp_pcadd : std_logic_vector(2 downto 0);--- ---

signal sram_data_out	: std_logic_vector(7 downto 0);

BEGIN
----------------------------------------------------------------------------
---     system clk input----> 4 clk consist of one instruction           ---
----------------------------------------------------------------------------
PROCESS (sysclk)
BEGIN
	IF sysrest = '1' THEN
		cntp <= "00";				
    ELSIF (sysclk'event AND sysclk = '1') THEN
	    cntp <= cntp + 1;
	END IF;			
END PROCESS;

with cntp select
      t <= "0001" when "00",   --- t[0]--->t1	
           "0010" when "01",   --- t[1]--->t2
           "0100" when "10",   --- t[2]--->t3
           "1000" when others;  --- t[3]--->t4
--------------- system clk end -----------------------------------------------
A0:
   FOR i in 0 to 7 generate
      temp_muxa(0,i) <= sram_data_out(i);
      temp_muxb(0,i) <= sram_data_out(i);
      temp_muxa(12,i) <= iopt0(i);
      temp_muxb(12,i) <= iopt0(i);
      temp_muxa(13,i) <= iopt1(i);
      temp_muxb(13,i) <= iopt1(i);
      temp_muxa(14,i) <= iopt2(i);
      temp_muxb(14,i) <= iopt2(i);
      temp_muxa(15,i) <= iopt3(i);
      temp_muxb(15,i) <= iopt3(i);
   end generate;
muxab: 
      FOR j IN 1 TO 11 GENERATE
         muxbb:
           for i in 0 to 7 generate
               temp_muxa(j,i) <= rgg(j)(i);
               temp_muxb(j,i) <= rgg(j)(i);
           end generate;
      END GENERATE;
---------------------------------------------------
prom : lpm_rom
        GENERIC MAP(LPM_WIDTH =>16,LPM_WIDTHAD => 8,LPM_FILE =>"prog5p.mif",LPM_ADDRESS_CONTROL => "UNREGISTERED",
                    LPM_OUTDATA => "UNREGISTERED")
        PORT MAP(address => pc(7 downto 0), q => pd);
sram : lpm_ram_dq
       GENERIC MAP(LPM_WIDTH=>8,LPM_WIDTHAD=>8,LPM_INDATA=>"REGISTERED",LPM_ADDRESS_CONTROL=>"UNREGISTERED",
                   LPM_OUTDATA=>"UNREGISTERED")
       PORT MAP(address=>rgg(1),data=>rdi,we=>swen,inclock=>sysclk,q=>sram_data_out);
muxa : lpm_mux
       GENERIC MAP(LPM_WIDTH  => 8,
                   LPM_WIDTHS => 4,
                   LPM_SIZE   => 16)
       PORT MAP(data   => temp_muxa,
                sel    => pdx(11 downto 8),
                result => muxa_result);
muxb : lpm_mux
       GENERIC MAP(LPM_WIDTH  => 8,
                   LPM_WIDTHS => 4,
                   LPM_SIZE   => 16)
       PORT MAP(data   => temp_muxb,
                sel    => pdx(7 downto 4),
                result => muxb_result);

-------------------------------------------------
PROCESS(sysclk)
BEGIN
  
  WAIT UNTIL (sysclk'EVENT) AND (sysclk='1'); 
     rqab <= muxa_result;
     pdx <= pd;    
     rdi <= alo(7 downto 0);
     ----------------------------------
     IF aldb='1' THEN
        rqbb <= pdx(7 downto 0);
     else
        rqbb <= muxb_result; --- note: muxb_result=rqb ---------
     end if;
     -----------------------------------
     FOR i IN 0 TO 15 LOOP
         IF wen='1' AND ws=i AND t(3)='1'THEN
            rgg(i) <= rdi;
         ELSE
            rgg(i)<=rgg(i);
         END IF;
     END LOOP;
     -------------------------------------
     FOR i IN 0 TO 3 LOOP
        IF pushst='1' AND sp=i AND t(3)='1' THEN
           stk(i) <= pc(11 downto 0) +1;
        ELSE
           stk(i)<= stk(i);
        END IF;
     END LOOP;
     ------------------------------------
     IF pcmx='1' AND t(2)='1' THEN
       sp <= sp+1;
     ELSIF pushst='1' AND t(3)='1' THEN
       sp <= sp-1;
     ELSE
       sp <= sp;
     END IF;
    -------------------------------------
     --------------------------------------
     IF pcmx='1' AND t(3)='1' then  ---