module SDRAM_controller();

input clk;
input nRESET;
input [23:0] din;
output [23:0] dout;
input [1:0] cmd;
output ready;

output sclk;
output CKE;
output nCS;
output nRAS;
output nCAS;
output nWE;
output [3:0] DQM;
output [1:0] BA;
output [10:0] A;
inout [31:0] DQ;

wire clk;
wire nRESET;
wire [23:0] din;
reg [23:0] dout;
wire [1:0] cmd;
reg ready;

wire sclk;
wire CKE;
reg nCS;
reg nRAS;
reg nCAS;
reg nWE;
wire [3:0] DQM;
reg [1:0] BA;
reg [10:0] A;
wire [31:0] DQ;

//CKE,DQM,sclk
CKE <=1'b1;
DQm[3:0] <=4'b0000;
sclk <=clk;

//FSM
reg [4:0] state;
always @(posedge clk or negedge nRESET)
begin
	if(~nRESET)
		state <=`ST_INIT;
	else begin
		case(state):
		`ST_INIT: 	if(init_complete)
						state <=`ST_IDLE;
		`ST_IDLE:	case(cmd):
					WRITE:state <=`ST_BW;
					READ:state <=`ST_READ;
					REFRESH:state <=`ST_RFR;
					default:state <=`ST_IDLE;
					endcase;				
		`ST_WRITE:	if(write_complete)
					state <=`ST_PCH;
		`ST_READ:	if(read_complete)
					state <=`ST_PCH;
		`ST_RFR:	if(refresh_complete)
					state <=`ST_IDLE;
		`ST_PCH:	if(precharge_complete)
					state <=`ST_IDLE;
		default:	state <=`ST_INIT;
		endcase;																						
	end
end	

/*this module is not completed yet.I can just give you a FSM for refrence.
More details should be available through yours' carefully consideration.
Pls note:1.you should convert 24bit data into 32 bit SDRAM data, and vice versa,maybe a fifo should be employed.
		 2.It is recommended that BURST write/read are employed to get the best performance for bandwidth.
		 3.The burst length shall be 8 or 16 or more.
		 4.As far as I know, video clk maybe 27MHz,so pls calculate the bandwidth required carefully, it is
		   a very important factor when you choosing your implementation.
		 5.cmd is external signal for SDRAM controller,00--write(burst),01--read(burst),11--auto refresh,when 
		   refresh counter gets to zero.The initial value of refresh counter should be determmined carefully.
		 6.sclk is the SDRAM working clock.It should be much faster than the module input clk.You should utilize
		   the Altera FPGA internal PLL to fulfill this clk,and plse note the phase shift of the 2 clocks.
		 7.When SDRAM is idle,the controller should give out a signal named as "ready",which means to external
		   logic that after this siganl's assertion external logic can give next read/write/refresh command. 
		 8.Maybe this FSM is still not totally correct yet.Pls modify it when you find there is any error.
		 9.ST_INIT--initialization and load mode register,
		   ST_IDLE--SDRAM controller is idle,
		   ST_WRITE,ST_READ,ST_REFRESH--once receiving corresponding command these states are entered, 
		   and corresponding commands(active,write/read...) are executed after-a-while.
		   ST_PCH:precharge state.		   
*/