//////////////////////////////////////////////////////////////////////////                                                              ////////  Generic Single-Port Synchronous RAM                         ////////                                                              ////////  This file is part of memory library available from          ////////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////////                                                              ////////  Description                                                 ////////  This block is a wrapper with common single-port             ////////  synchronous memory interface for different                  ////////  types of ASIC and FPGA RAMs. Beside universal memory        ////////  interface it also provides behavioral model of generic      ////////  single-port synchronous RAM.                                ////////  It should be used in all OPENCORES designs that want to be  ////////  portable accross different target technologies and          ////////  independent of target memory.                               ////////                                                              ////////  Supported ASIC RAMs are:                                    ////////  - Artisan Single-Port Sync RAM                              ////////  - Avant! Two-Port Sync RAM (*)                              ////////  - Virage Single-Port Sync RAM                               ////////  - Virtual Silicon Single-Port Sync RAM                      ////////                                                              ////////  Supported FPGA RAMs are:                                    ////////  - Xilinx Virtex RAMB4_S16                                   ////////  - Altera LPM                                                ////////                                                              ////////  To Do:                                                      ////////   - xilinx rams need external tri-state logic                ////////   - fix avant! two-port ram                                  ////////   - add additional RAMs                                      ////////                                                              ////////  Author(s):                                                  ////////      - Damjan Lampret, lampret@opencores.org                 ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: or1200_spram_256x21.v,v $// Revision 1.3  2003/04/07 01:19:07  lampret// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.//// Revision 1.2  2002/10/17 20:04:40  lampret// Added BIST scan. Special VS RAMs need to be used to implement BIST.//// Revision 1.1  2002/01/03 08:16:15  lampret// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.//// Revision 1.10  2001/11/27 21:24:04  lampret// Changed instantiation name of VS RAMs.//// Revision 1.9  2001/11/27 19:45:04  lampret// Fixed VS RAM instantiation - again.//// Revision 1.8  2001/11/23 21:42:31  simons// Program counter divided to PPC and NPC.//// Revision 1.6  2001/10/21 17:57:16  lampret// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.//// Revision 1.5  2001/10/14 13:12:09  lampret// MP3 version.//// Revision 1.1.1.1  2001/10/06 10:18:36  igorm// no message//// Revision 1.1  2001/08/09 13:39:33  lampret// Major clean-up.//// Revision 1.2  2001/07/30 05:38:02  lampret// Adding empty directories required by HDL coding guidelines////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "or1200_defines.v"module or1200_spram_256x21(`ifdef OR1200_BIST	// RAM BIST	scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`endif	// Generic synchronous single-port RAM interface	clk, rst, ce, we, oe, addr, di, do);//// Default address and data buses width//parameter aw = 8;parameter dw = 21;`ifdef OR1200_BIST//// RAM BIST//input			scanb_rst,			scanb_si,			scanb_en,			scanb_clk;output			scanb_so;`endif//// Generic synchronous single-port RAM interface//input			clk;	// Clockinput			rst;	// Resetinput			ce;	// Chip enable inputinput			we;	// Write enable inputinput			oe;	// Output enable inputinput 	[aw-1:0]	addr;	// address bus inputsinput	[dw-1:0]	di;	// input data busoutput	[dw-1:0]	do;	// output data bus//// Internal wires and registers//wire	[10:0]		unconnected;`ifdef OR1200_VIRTUALSILICON_SSP`else`ifdef OR1200_BISTassign scanb_so = scanb_si;`endif`endif`ifdef OR1200_ARTISAN_SSP//// Instantiation of ASIC memory://// Artisan Synchronous Single-Port RAM (ra1sh)//`ifdef UNUSEDart_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(`elseart_hssp_256x21 artisan_ssp(`endif	.clk(clk),	.cen(~ce),	.wen(~we),	.a(addr),	.d(di),	.oen(~oe),	.q(do));`else`ifdef OR1200_AVANT_ATP//// Instantiation of ASIC memory://// Avant! Asynchronous Two-Port RAM//avant_atp avant_atp(	.web(~we),	.reb(),	.oeb(~oe),	.rcsb(),	.wcsb(),	.ra(addr),	.wa(addr),	.di(di),	.do(do));`else`ifdef OR1200_VIRAGE_SSP//// Instantiation of ASIC memory://// Virage Synchronous 1-port R/W RAM//virage_ssp virage_ssp(	.clk(clk),	.adr(addr),	.d(di),	.we(we),	.oe(oe),	.me(ce),	.q(do));`else`ifdef OR1200_VIRTUALSILICON_SSP//// Instantiation of ASIC memory://// Virtual Silicon Single-Port Synchronous SRAM//`ifdef UNUSEDvs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(`else`ifdef OR1200_BISTvs_hdsp_256x21_bist vs_ssp(`elsevs_hdsp_256x21 vs_ssp(`endif`endif`ifdef OR1200_BIST	// RAM BIST	.scanb_rst(scanb_rst),	.scanb_si(scanb_si),	.scanb_so(scanb_so),	.scanb_en(scanb_en),	.scanb_clk(scanb_clk),`endif	.CK(clk),	.ADR(addr),	.DI(di),	.WEN(~we),	.CEN(~ce),	.OEN(~oe),	.DOUT(do));`else`ifdef OR1200_XILINX_RAMB4//// Instantiation of FPGA memory://// Virtex/Spartan2////// Block 0//RAMB4_S16 ramb4_s16_0(	.CLK(clk),	.RST(rst),	.ADDR(addr),	.DI(di[15:0]),	.EN(ce),	.WE(we),	.DO(do[15:0]));//// Block 1//RAMB4_S16 ramb4_s16_1(	.CLK(clk),	.RST(rst),	.ADDR(addr),	.DI({11'b00000000000, di[20:16]}),	.EN(ce),	.WE(we),	.DO({unconnected, do[20:16]}));`else`ifdef OR1200_ALTERA_LPM//// Instantiation of FPGA memory://// Altera LPM//// Added By Jamil Khatib//wire    wr;assign  wr = ce & we;initial $display("Using Altera LPM.");lpm_ram_dq lpm_ram_dq_component (        .address(addr),        .inclock(clk),        .outclock(clk),        .data(di),        .we(wr),        .q(do));defparam lpm_ram_dq_component.lpm_width = dw,        lpm_ram_dq_component.lpm_widthad = aw,        lpm_ram_dq_component.lpm_indata = "REGISTERED",        lpm_ram_dq_component.lpm_address_control = "REGISTERED",        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";        // examplar attribute lpm_ram_dq_component NOOPT TRUE`else//// Generic single-port synchronous RAM model////// Generic RAM's registers and wires//reg	[dw-1:0]	mem [(1<<aw)-1:0];	// RAM contentreg	[dw-1:0]	do_reg;			// RAM data output register//// Data output drivers//assign do = (oe) ? do_reg : {dw{1'b0}};//// RAM read and write//always @(posedge clk)	if (ce && !we)		do_reg <= #1 mem[addr];	else if (ce && we)		mem[addr] <= #1 di;`endif	// !OR1200_ALTERA_LPM`endif	// !OR1200_XILINX_RAMB4_S16`endif	// !OR1200_VIRTUALSILICON_SSP`endif	// !OR1200_VIRAGE_SSP`endif  // !OR1200_AVANT_ATP`endif	// !OR1200_ARTISAN_SSPendmodule