//////////////////////////////////////////////////////////////////////////                                                              ////////  OR1200 Top Level                                            ////////                                                              ////////  This file is part of the OpenRISC 1200 project              ////////  http://www.opencores.org/cores/or1k/                        ////////                                                              ////////  Description                                                 ////////  OR1200 Top Level                                            ////////                                                              ////////  To Do:                                                      ////////   - make it smaller and faster                               ////////                                                              ////////  Author(s):                                                  ////////      - Damjan Lampret, lampret@opencores.org                 ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: or1200_top.v,v $// Revision 1.10  2002/12/08 08:57:56  lampret// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.//// Revision 1.9  2002/10/17 20:04:41  lampret// Added BIST scan. Special VS RAMs need to be used to implement BIST.//// Revision 1.8  2002/08/18 19:54:22  lampret// Added store buffer.//// Revision 1.7  2002/07/14 22:17:17  lampret// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.//// Revision 1.6  2002/03/29 15:16:56  lampret// Some of the warnings fixed.//// Revision 1.5  2002/02/11 04:33:17  lampret// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.//// Revision 1.4  2002/02/01 19:56:55  lampret// Fixed combinational loops.//// Revision 1.3  2002/01/28 01:16:00  lampret// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.//// Revision 1.2  2002/01/18 07:56:00  lampret// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.//// Revision 1.1  2002/01/03 08:16:15  lampret// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.//// Revision 1.13  2001/11/23 08:38:51  lampret// Changed DSR/DRR behavior and exception detection.//// Revision 1.12  2001/11/20 00:57:22  lampret// Fixed width of du_except.//// Revision 1.11  2001/11/18 08:36:28  lampret// For GDB changed single stepping and disabled trap exception.//// Revision 1.10  2001/10/21 17:57:16  lampret// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.//// Revision 1.9  2001/10/14 13:12:10  lampret// MP3 version.//// Revision 1.1.1.1  2001/10/06 10:18:35  igorm// no message//// Revision 1.4  2001/08/13 03:36:20  lampret// Added cfg regs. Moved all defines into one defines.v file. More cleanup.//// Revision 1.3  2001/08/09 13:39:33  lampret// Major clean-up.//// Revision 1.2  2001/07/22 03:31:54  lampret// Fixed RAM's oen bug. Cache bypass under development.//// Revision 1.1  2001/07/20 00:46:21  lampret// Development version of RTL. Libraries are missing.////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "or1200_defines.v"module or1200_top(	// System	clk_i, rst_i, pic_ints_i, clmode_i,	// Instruction WISHBONE INTERFACE	iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,	iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,`ifdef OR1200_WB_CAB	iwb_cab_o,`endif`ifdef OR1200_WB_B3	iwb_cti_o, iwb_bte_o,`endif	// Data WISHBONE INTERFACE	dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,	dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,`ifdef OR1200_WB_CAB	dwb_cab_o,`endif`ifdef OR1200_WB_B3	dwb_cti_o, dwb_bte_o,`endif	// External Debug Interface	dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,	dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o,	`ifdef OR1200_BIST	// RAM BIST	scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`endif	// Power Management	pm_cpustall_i,	pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o, 	pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o);parameter dw = `OR1200_OPERAND_WIDTH;parameter aw = `OR1200_OPERAND_WIDTH;parameter ppic_ints = `OR1200_PIC_INTS;//// I/O////// System//input			clk_i;input			rst_i;input	[1:0]		clmode_i;	// 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4input	[ppic_ints-1:0]	pic_ints_i;//// Instruction WISHBONE interface//input			iwb_clk_i;	// clock inputinput			iwb_rst_i;	// reset inputinput			iwb_ack_i;	// normal terminationinput			iwb_err_i;	// termination w/ errorinput			iwb_rty_i;	// termination w/ retryinput	[dw-1:0]	iwb_dat_i;	// input data busoutput			iwb_cyc_o;	// cycle valid outputoutput	[aw-1:0]	iwb_adr_o;	// address bus outputsoutput			iwb_stb_o;	// strobe outputoutput			iwb_we_o;	// indicates write transferoutput	[3:0]		iwb_sel_o;	// byte select outputsoutput	[dw-1:0]	iwb_dat_o;	// output data bus`ifdef OR1200_WB_CABoutput			iwb_cab_o;	// indicates consecutive address burst`endif`ifdef OR1200_WB_B3output	[2:0]		iwb_cti_o;	// cycle type identifieroutput	[1:0]		iwb_bte_o;	// burst type extension`endif//// Data WISHBONE interface//input			dwb_clk_i;	// clock inputinput			dwb_rst_i;	// reset inputinput			dwb_ack_i;	// normal terminationinput			dwb_err_i;	// termination w/ errorinput			dwb_rty_i;	// termination w/ retryinput	[dw-1:0]	dwb_dat_i;	// input data busoutput			dwb_cyc_o;	// cycle valid outputoutput	[aw-1:0]	dwb_adr_o;	// address bus outputsoutput			dwb_stb_o;	// strobe outputoutput			dwb_we_o;	// indicates write transferoutput	[3:0]		dwb_sel_o;	// byte select outputsoutput	[dw-1:0]	dwb_dat_o;	// output data bus`ifdef OR1200_WB_CABoutput			dwb_cab_o;	// indicates consecutive address burst`endif`ifdef OR1200_WB_B3output	[2:0]		dwb_cti_o;	// cycle type identifieroutput	[1:0]		dwb_bte_o;	// burst type extension`endif//// External Debug Interface//input			dbg_stall_i;	// External Stall Inputinput	[dw-1:0]	dbg_dat_i;	// External Data Inputinput	[aw-1:0]	dbg_adr_i;	// External Address Inputinput	[2:0]		dbg_op_i;	// External Operation Select Inputinput			dbg_ewt_i;	// External Watchpoint Trigger Inputoutput	[3:0]		dbg_lss_o;	// External Load/Store Unit Statusoutput	[1:0]		dbg_is_o;	// External Insn Fetch Statusoutput	[10:0]		dbg_wp_o;	// Watchpoints Outputsoutput			dbg_bp_o;	// Breakpoint Outputoutput	[dw-1:0]	dbg_dat_o;	// External Data Output`ifdef OR1200_BIST//// RAM BIST//input			scanb_rst,			scanb_si,			scanb_en,			scanb_clk;output			scanb_so;`endif//// Power Management//input			pm_cpustall_i;output	[3:0]		pm_clksd_o;output			pm_dc_gate_o;output			pm_ic_gate_o;output			pm_dmmu_gate_o;output			pm_immu_gate_o;output			pm_tt_gate_o;output			pm_cpu_gate_o;output			pm_wakeup_o;output			pm_lvolt_o;//// Internal wires and regs////// DC to SB//wire	[dw-1:0]	dcsb_dat_dc;wire	[aw-1:0]	dcsb_adr_dc;wire			dcsb_cyc_dc;wire			dcsb_stb_dc;wire			dcsb_we_dc;wire	[3:0]		dcsb_sel_dc;wire			dcsb_cab_dc;wire	[dw-1:0]	dcsb_dat_sb;wire			dcsb_ack_sb;wire			dcsb_err_sb;//// SB to BIU//wire	[dw-1:0]	sbbiu_dat_sb;wire	[aw-1:0]	sbbiu_adr_sb;wire			sbbiu_cyc_sb;wire			sbbiu_stb_sb;wire			sbbiu_we_sb;wire	[3:0]		sbbiu_sel_sb;wire			sbbiu_cab_sb;wire	[dw-1:0]	sbbiu_dat_biu;wire			sbbiu_ack_biu;wire			sbbiu_err_biu;//// IC to BIU//wire	[dw-1:0]	icbiu_dat_ic;wire	[aw-1:0]	icbiu_adr_ic;wire			icbiu_cyc_ic;wire			icbiu_stb_ic;wire			icbiu_we_ic;wire	[3:0]		icbiu_sel_ic;wire	[3:0]		icbiu_tag_ic;wire	[dw-1:0]	icbiu_dat_biu;wire			icbiu_ack_biu;wire			icbiu_err_biu;wire	[3:0]		icbiu_tag_biu;//// CPU's SPR access to various RISC units (shared wires)//wire			supv;wire	[aw-1:0]	spr_addr;wire	[dw-1:0]	spr_dat_cpu;wire	[31:0]		spr_cs;wire			spr_we;//// DMMU and CPU//wire			dmmu_en;wire	[31:0]		spr_dat_dmmu;//// DMMU and DC//wire			dcdmmu_err_dc;wire	[3:0]		dcdmmu_tag_dc;wire	[aw-1:0]	dcdmmu_adr_dmmu;wire			dcdmmu_cycstb_dmmu;wire			dcdmmu_ci_dmmu;//// CPU and data memory subsystem//wire			dc_en;wire	[31:0]		dcpu_adr_cpu;wire			dcpu_we_cpu;wire	[3:0]		dcpu_sel_cpu;wire	[3:0]		dcpu_tag_cpu;wire	[31:0]		dcpu_dat_cpu;wire	[31:0]		dcpu_dat_dc;wire			dcpu_ack_dc;wire			dcpu_rty_dc;wire			dcpu_err_dmmu;wire	[3:0]		dcpu_tag_dmmu;//// IMMU and CPU//wire			immu_en;wire	[31:0]		spr_dat_immu;//// CPU and insn memory subsystem//wire			ic_en;wire	[31:0]		icpu_adr_cpu;wire			icpu_cycstb_cpu;wire	[3:0]		icpu_sel_cpu;wire	[3:0]		icpu_tag_cpu;wire	[31:0]		icpu_dat_ic;wire			icpu_ack_ic;wire	[31:0]		icpu_adr_immu;wire			icpu_err_immu;wire	[3:0]		icpu_tag_immu;//// IMMU and IC//wire	[aw-1:0]	icimmu_adr_immu;wire			icimmu_rty_ic;wire			icimmu_err_ic;wire	[3:0]		icimmu_tag_ic;wire			icimmu_cycstb_immu;wire			icimmu_ci_immu;//// Connection between CPU and PIC//wire	[dw-1:0]	spr_dat_pic;wire			pic_wakeup;wire			sig_int;//// Connection between CPU and PM//wire	[dw-1:0]	spr_dat_pm;//// CPU and TT//wire	[dw-1:0]	spr_dat_tt;wire			sig_tick;//// Debug port and caches/MMUs//wire	[dw-1:0]	spr_dat_du;wire			du_stall;wire	[dw-1:0]	du_addr;wire	[dw-1:0]	du_dat_du;wire			du_read;wire			du_write;wire	[12:0]		du_except;wire	[`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;wire	[dw-1:0]	du_dat_cpu;wire			ex_freeze;wire	[31:0]		ex_insn;wire	[`OR1200_BRANCHOP_WIDTH-1:0]	branch_op;wire	[31:0]		spr_dat_npc;wire	[31:0]		rf_dataw;`ifdef OR1200_BIST//// RAM BIST//wire			scanb_immu_so;wire			scanb_ic_so;wire			scanb_dmmu_so;wire			scanb_dc_so;wire			scanb_immu_si = scanb_si;wire			scanb_ic_si = scanb_immu_so;wire			scanb_dmmu_si = scanb_ic_so;wire			scanb_dc_si = scanb_dmmu_so;assign			scanb_so = scanb_dc_so;`endif//// Instantiation of Instruction WISHBONE BIU//or1200_wb_biu iwb_biu(	// RISC clk, rst and clock control	.clk(clk_i),	.rst(rst_i),	.clmode(clmode_i),	// WISHBONE interface	.wb_clk_i(iwb_clk_i),	.wb_rst_i(iwb_rst_i),	.wb_ack_i(iwb_ack_i),	.wb_err_i(iwb_err_i),	.wb_rty_i(iwb_rty_i),	.wb_dat_i(iwb_dat_i),	.wb_cyc_o(iwb_cyc_o),	.wb_adr_o(iwb_adr_o),	.wb_stb_o(iwb_stb_o),	.wb_we_o(iwb_we_o),	.wb_sel_o(iwb_sel_o),	.wb_dat_o(iwb_dat_o),`ifdef OR1200_WB_CAB	.wb_cab_o(iwb_cab_o),`endif`ifdef OR1200_WB_B3	.wb_cti_o(iwb_cti_o),	.wb_bte_o(iwb_bte_o),`endif	// Internal RISC bus	.biu_dat_i(icbiu_dat_ic),	.biu_adr_i(icbiu_adr_ic),