//////////////////////////////////////////////////////////////////////////                                                              ////////  OR1200's IC RAMs                                            ////////                                                              ////////  This file is part of the OpenRISC 1200 project              ////////  http://www.opencores.org/cores/or1k/                        ////////                                                              ////////  Description                                                 ////////  Instantiation of Instruction cache data rams                ////////                                                              ////////  To Do:                                                      ////////   - make it smaller and faster                               ////////                                                              ////////  Author(s):                                                  ////////      - Damjan Lampret, lampret@opencores.org                 ////////                                                              //////////////////////////////////////////////////////////////////////////////                                                              //////// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////////                                                              //////// This source file may be used and distributed without         //////// restriction provided that this copyright statement is not    //////// removed from the file and that any derivative work contains  //////// the original copyright notice and the associated disclaimer. ////////                                                              //////// This source file is free software; you can redistribute it   //////// and/or modify it under the terms of the GNU Lesser General   //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any   //////// later version.                                               ////////                                                              //////// This source is distributed in the hope that it will be       //////// useful, but WITHOUT ANY WARRANTY; without even the implied   //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      //////// PURPOSE.  See the GNU Lesser General Public License for more //////// details.                                                     ////////                                                              //////// You should have received a copy of the GNU Lesser General    //////// Public License along with this source; if not, download it   //////// from http://www.opencores.org/lgpl.shtml                     ////////                                                              ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: or1200_ic_ram.v,v $// Revision 1.2  2002/10/17 20:04:40  lampret// Added BIST scan. Special VS RAMs need to be used to implement BIST.//// Revision 1.1  2002/01/03 08:16:15  lampret// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.//// Revision 1.9  2001/10/21 17:57:16  lampret// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.//// Revision 1.8  2001/10/14 13:12:09  lampret// MP3 version.//// Revision 1.1.1.1  2001/10/06 10:18:36  igorm// no message//// Revision 1.3  2001/08/09 13:39:33  lampret// Major clean-up.//// Revision 1.2  2001/07/22 03:31:54  lampret// Fixed RAM's oen bug. Cache bypass under development.//// Revision 1.1  2001/07/20 00:46:03  lampret// Development version of RTL. Libraries are missing.////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "or1200_defines.v"module or1200_ic_ram(	// Clock and reset	clk, rst, `ifdef OR1200_BIST	// RAM BIST	scanb_rst, scanb_si, scanb_so, scanb_en, scanb_clk,`endif	// Internal i/f	addr, en, we, datain, dataout);parameter dw = `OR1200_OPERAND_WIDTH;parameter aw = `OR1200_ICINDX;//// I/O//input 				clk;input				rst;input	[aw-1:0]		addr;input				en;input	[3:0]			we;input	[dw-1:0]		datain;output	[dw-1:0]		dataout;`ifdef OR1200_BIST//// RAM BIST//input				scanb_rst,				scanb_si,				scanb_en,				scanb_clk;output				scanb_so;`endif`ifdef OR1200_NO_IC//// Insn cache not implemented//assign dataout = {dw{1'b0}};`ifdef OR1200_BISTassign scanb_so = scanb_si;`endif`else//// Instantiation of IC RAM block//`ifdef OR1200_IC_1W_4KBor1200_spram_1024x32 ic_ram0(`endif`ifdef OR1200_IC_1W_8KBor1200_spram_2048x32 ic_ram0(`endif`ifdef OR1200_BIST	// RAM BIST	.scanb_rst(scanb_rst),	.scanb_si(scanb_si),	.scanb_so(scanb_so),	.scanb_en(scanb_en),	.scanb_clk(scanb_clk),`endif	.clk(clk),	.rst(rst),	.ce(en),	.we(we[0]),	.oe(1'b1),	.addr(addr),	.di(datain),	.do(dataout));`endifendmodule