module m74148a(ei,i0,i1,i2,i3,i4,i5,i6,i7,a2,a1,a0,gs,eo);
input ei,i0,i1,i2,i3,i4,i5,i6,i7;
output a2,a1,a0,gs,eo;
reg a2,a1,a0,gs,eo;

always @(ei or i0 or i1 or i2 or i3 or i4 or i5 or i6 or i7)
if(ei==1)
	{a2,a1,a0,gs,eo}=5'b11111;
else
casex({i0,i1,i2,i3,i4,i5,i6,i7})
8'b11111111:{a2,a1,a0,gs,eo}=5'b11110;
8'bxxxxxxx0:{a2,a1,a0,gs,eo}=5'b00001;
8'bxxxxxx01:{a2,a1,a0,gs,eo}=5'b00101;
8'bxxxxx011:{a2,a1,a0,gs,eo}=5'b01001;
8'bxxxx0111:{a2,a1,a0,gs,eo}=5'b01101;
8'bxxx01111:{a2,a1,a0,gs,eo}=5'b10001;
8'bxx011111:{a2,a1,a0,gs,eo}=5'b10101;
8'bx0111111:{a2,a1,a0,gs,eo}=5'b11001;
8'b01111111:{a2,a1,a0,gs,eo}=5'b11101;
endcase

endmodule