-- file: clk_core.vhd-- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.-- -- This file contains confidential and proprietary information-- of Xilinx, Inc. and is protected under U.S. and-- international copyright and other intellectual property-- laws.-- -- DISCLAIMER-- This disclaimer is not a license and does not grant any-- rights to the materials distributed herewith. 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Customer assumes the sole risk and-- liability of any use of Xilinx products in Critical-- Applications, subject only to applicable laws and-- regulations governing limitations on product liability.-- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS-- PART OF THIS FILE AT ALL TIMES.-- -------------------------------------------------------------------------------- User entered comments-------------------------------------------------------------------------------- None---------------------------------------------------------------------------------- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)-------------------------------------------------------------------------------- CLK_OUT1    27.000      0.000      50.0      200.000     60.000-- CLK_OUT2    27.000      0.000      50.0      940.740     60.000---------------------------------------------------------------------------------- Input Clock   Input Freq (MHz)   Input Jitter (UI)-------------------------------------------------------------------------------- primary          27.000            0.010library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;use ieee.numeric_std.all;library unisim;use unisim.vcomponents.all;entity clk_core isport (-- Clock in ports  CLK_IN1           : in     std_logic;  -- Clock out ports  CLK_OUT1          : out    std_logic;  CLK_OUT2          : out    std_logic;  -- Status and control signals  RESET             : in     std_logic;  LOCKED            : out    std_logic );end clk_core;architecture xilinx of clk_core is  attribute CORE_GENERATION_INFO : string;  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_core,clk_wiz_v3_1,{component_name=clk_core,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=true}";	  -- Input clock buffering / unused connectors  signal clkin1            : std_logic;  -- Output clock buffering  signal clk_out1_internal : std_logic;  signal clkfb             : std_logic;  signal clk0              : std_logic;  signal clkfx             : std_logic;  signal clkfbout          : std_logic;  signal locked_internal   : std_logic;  signal status_internal   : std_logic_vector(7 downto 0);begin  -- Input buffering  --------------------------------------  clkin1_buf : IBUFG  port map   (O => clkin1,    I => CLK_IN1);  -- Clocking primitive  --------------------------------------    -- Instantiation of the DCM primitive  --    * Unused inputs are tied off  --    * Unused outputs are labeled unused  dcm_sp_inst: DCM_SP  generic map   (CLKDV_DIVIDE          => 2.000,    CLKFX_DIVIDE          => 2,    CLKFX_MULTIPLY        => 2,    CLKIN_DIVIDE_BY_2     => FALSE,    CLKIN_PERIOD          => 37.037,    CLKOUT_PHASE_SHIFT    => "NONE",    CLK_FEEDBACK          => "1X",    DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",    PHASE_SHIFT           => 0,    STARTUP_WAIT          => FALSE)  port map   -- Input clock   (CLKIN                 => clkin1,    CLKFB                 => clkfb,    -- Output clocks    CLK0                  => clk0,    CLK90                 => open,    CLK180                => open,    CLK270                => open,    CLK2X                 => open,    CLK2X180              => open,    CLKFX                 => clkfx,    CLKFX180              => open,    CLKDV                 => open,   -- Ports for dynamic phase shift    PSCLK                 => '0',    PSEN                  => '0',    PSINCDEC              => '0',    PSDONE                => open,   -- Other control and status signals    LOCKED                => locked_internal,    STATUS                => status_internal,    RST                   => RESET,   -- Unused pin, tie low    DSSEN                 => '0');  LOCKED                <= locked_internal;  -- Output buffering  -------------------------------------  clkfb <= clk_out1_internal;  clkout1_buf : BUFG  port map   (O   => clk_out1_internal,    I   => clk0);  CLK_OUT1 <= clk_out1_internal;  CLK_OUT2 <= clkfx;end xilinx;