REM file: implement.batREM REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.REM REM This file contains confidential and proprietary informationREM of Xilinx, Inc. and is protected under U.S. andREM international copyright and other intellectual propertyREM laws.REM REM DISCLAIMERREM This disclaimer is not a license and does not grant anyREM rights to the materials distributed herewith. Except asREM otherwise provided in a valid license issued to you byREM Xilinx, and to the maximum extent permitted by applicableREM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" ANDREM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIESREM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDINGREM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; andREM (2) Xilinx shall not be liable (whether in contract or tort,REM including negligence, or under any other theory ofREM liability) for any loss or damage of any kind or natureREM related to, arising under or in connection with theseREM materials, including for any direct, or any indirect,REM special, incidental, or consequential loss or damageREM (including loss of data, profits, goodwill, or any type ofREM loss or damage suffered as a result of any action broughtREM by a third party) even if such damage or loss wasREM reasonably foreseeable or Xilinx had been advised of theREM possibility of the same.REM REM CRITICAL APPLICATIONSREM Xilinx products are not designed or intended to be fail-REM safe, or for use in any application requiring fail-safeREM performance, such as life-support or safety devices orREM systems, Class III medical devices, nuclear facilities,REM applications related to the deployment of airbags, or anyREM other applications that could lead to death, personalREM injury, or severe property or environmental damageREM (individually and collectively, "CriticalREM Applications"). Customer assumes the sole risk andREM liability of any use of Xilinx products in CriticalREM Applications, subject only to applicable laws andREM regulations governing limitations on product liability.REM REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED ASREM PART OF THIS FILE AT ALL TIMES.REM REM -----------------------------------------------------------------------------REM  Script to synthesize and implement the RTL provided for the clocking wizardREM -----------------------------------------------------------------------------REM Clean up the results directoryrmdir /S /Q resultsmkdir resultsREM Copy unisim_comp.v file to results directorycopy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\REM Synthesize the Verilog Wrapper Filesecho 'Synthesizing Clocking Wizard design with XST'xst -ifn xst.scrcopy clk_core_exdes.ngc results\REM  Copy the constraints files generated by Coregenecho 'Copying files from constraints directory to results directory'copy ..\clk_core.ucf results\cd resultsecho 'Running ngdbuild'ngdbuild -uc clk_core.ucf clk_core_exdesecho 'Running map'map -timing -pr b clk_core_exdes -o mapped.ncdecho 'Running par'par -w mapped.ncd routed mapped.pcfecho 'Running trce'trce -e 10 routed -o routed mapped.pcfecho 'Running design through bitgen'bitgen -w routedecho 'Running netgen to create gate level model for the clocking wizard example design'netgen -ofmt verilog -sim -tm clk_core_exdes -w routed.ncd routed.vcd ..