#!/bin/sh# file: implement.sh# # (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.# # This file contains confidential and proprietary information# of Xilinx, Inc. and is protected under U.S. and# international copyright and other intellectual property# laws.# # DISCLAIMER# This disclaimer is not a license and does not grant any# rights to the materials distributed herewith. Except as# otherwise provided in a valid license issued to you by# Xilinx, and to the maximum extent permitted by applicable# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and# (2) Xilinx shall not be liable (whether in contract or tort,# including negligence, or under any other theory of# liability) for any loss or damage of any kind or nature# related to, arising under or in connection with these# materials, including for any direct, or any indirect,# special, incidental, or consequential loss or damage# (including loss of data, profits, goodwill, or any type of# loss or damage suffered as a result of any action brought# by a third party) even if such damage or loss was# reasonably foreseeable or Xilinx had been advised of the# possibility of the same.# # CRITICAL APPLICATIONS# Xilinx products are not designed or intended to be fail-# safe, or for use in any application requiring fail-safe# performance, such as life-support or safety devices or# systems, Class III medical devices, nuclear facilities,# applications related to the deployment of airbags, or any# other applications that could lead to death, personal# injury, or severe property or environmental damage# (individually and collectively, "Critical# Applications"). Customer assumes the sole risk and# liability of any use of Xilinx products in Critical# Applications, subject only to applicable laws and# regulations governing limitations on product liability.# # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS# PART OF THIS FILE AT ALL TIMES.# #-----------------------------------------------------------------------------# Script to synthesize and implement the RTL provided for the clocking wizard#-----------------------------------------------------------------------------# Clean up the results directoryrm -rf resultsmkdir results# Copy unisim_comp.v file to results directorycp $XILINX/verilog/src/iSE/unisim_comp.v ./results/# Synthesize the Verilog Wrapper Filesecho 'Synthesizing Clocking Wizard design with XST'xst -ifn xst.scrcp clk_core_exdes.ngc results/#  Copy the constraints files generated by Coregenecho 'Copying files from constraints directory to results directory'cp ../clk_core.ucf results/cd resultsecho 'Running ngdbuild'ngdbuild -uc clk_core.ucf clk_core_exdesecho 'Running map'map -timing clk_core_exdes -o mapped.ncdecho 'Running par'par -w mapped.ncd routed mapped.pcfecho 'Running trce'trce -e 10 routed -o routed mapped.pcfecho 'Running design through bitgen'bitgen -w routedecho 'Running netgen to create gate level model for the clocking wizard example design'netgen -ofmt verilog -sim -tm clk_core_exdes -w routed.ncd routed.vcd ..