// file: clk_core.v// // (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.// // This file contains confidential and proprietary information// of Xilinx, Inc. and is protected under U.S. and// international copyright and other intellectual property// laws.// // DISCLAIMER// This disclaimer is not a license and does not grant any// rights to the materials distributed herewith. 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Customer assumes the sole risk and// liability of any use of Xilinx products in Critical// Applications, subject only to applicable laws and// regulations governing limitations on product liability.// // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS// PART OF THIS FILE AT ALL TIMES.// //----------------------------------------------------------------------------// User entered comments//----------------------------------------------------------------------------// None////----------------------------------------------------------------------------// Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase// Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)//----------------------------------------------------------------------------// CLK_OUT1    27.000      0.000      50.0      200.000     60.000// CLK_OUT2    27.000      0.000      50.0      940.740     60.000////----------------------------------------------------------------------------// Input Clock   Input Freq (MHz)   Input Jitter (UI)//----------------------------------------------------------------------------// primary          27.000            0.010`timescale 1ps/1ps(* CORE_GENERATION_INFO = "clk_core,clk_wiz_v3_1,{component_name=clk_core,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=true}" *)module clk_core (// Clock in ports  input         CLK_IN1,  // Clock out ports  output        CLK_OUT1,  output        CLK_OUT2,  // Status and control signals  input         RESET,  output        LOCKED );  // Input buffering  //------------------------------------  IBUFG clkin1_buf   (.O (clkin1),    .I (CLK_IN1));  // Clocking primitive  //------------------------------------  // Instantiation of the DCM primitive  //    * Unused inputs are tied off  //    * Unused outputs are labeled unused  wire        psdone_unused;  wire        locked_int;  wire [7:0]  status_int;  wire clkfb;  wire clk0;  wire clkfx;  DCM_SP  #(.CLKDV_DIVIDE          (2.000),    .CLKFX_DIVIDE          (2),    .CLKFX_MULTIPLY        (2),    .CLKIN_DIVIDE_BY_2     ("FALSE"),    .CLKIN_PERIOD          (37.037),    .CLKOUT_PHASE_SHIFT    ("NONE"),    .CLK_FEEDBACK          ("1X"),    .DESKEW_ADJUST         ("SYSTEM_SYNCHRONOUS"),    .PHASE_SHIFT           (0),    .STARTUP_WAIT          ("FALSE"))  dcm_sp_inst    // Input clock   (.CLKIN                 (clkin1),    .CLKFB                 (clkfb),    // Output clocks    .CLK0                  (clk0),    .CLK90                 (),    .CLK180                (),    .CLK270                (),    .CLK2X                 (),    .CLK2X180              (),    .CLKFX                 (clkfx),    .CLKFX180              (),    .CLKDV                 (),    // Ports for dynamic phase shift    .PSCLK                 (1'b0),    .PSEN                  (1'b0),    .PSINCDEC              (1'b0),    .PSDONE                (),    // Other control and status signals    .LOCKED                (locked_int),    .STATUS                (status_int),     .RST                   (RESET),    // Unused pin- tie low    .DSSEN                 (1'b0));    assign LOCKED = locked_int;  // Output buffering  //-----------------------------------  assign clkfb = CLK_OUT1;  BUFG clkout1_buf   (.O   (CLK_OUT1),    .I   (clk0));  assign CLK_OUT2 = clkfx;endmodule