`timescale 1ns/1nsmodule lpm_mult ( result, dataa, datab, sum, clock, clken, aclr ) ;  parameter lpm_type       = "lpm_mult" ;  parameter lpm_widtha     = 8 ;  parameter lpm_widthb     = 8 ;  parameter lpm_widths     = 8 ;  parameter lpm_widthp     = 16 ;  parameter lpm_representation  = "UNSIGNED" ;  parameter lpm_pipeline   = 0 ;  parameter lpm_hint = "UNUSED" ;  input  clock ;  input  clken ;  input  aclr ;  input  [lpm_widtha-1:0] dataa ;  input  [lpm_widthb-1:0] datab ;  input  [lpm_widths-1:0] sum ;  output [lpm_widthp-1:0] result;  // inernal reg  reg   [lpm_widthp-1:0] tmp_result ;  reg   [lpm_widthp-1:0] tmp_result2 [lpm_pipeline-3:0];  reg   [lpm_widtha-1:0] a_int ;  reg   [lpm_widthb-1:0] b_int ;  reg   [lpm_widths-1:0] s_int ;  reg   [lpm_widthp-1:0] p_reg ;  integer p_int;  integer i, j, k, m, n, p, maxs_mn ;  integer int_dataa, int_datab, int_sum, int_result ;  always @( dataa or datab or sum)	begin		if (lpm_representation == "UNSIGNED")			begin				int_dataa = dataa ;				int_datab = datab ;				int_sum = sum ;			end		else 			if (lpm_representation == "SIGNED")				begin					// convert signed dataa					if(dataa[lpm_widtha-1] == 1)						begin							int_dataa = 0 ;							for(i = 0; i < lpm_widtha - 1; i = i + 1)								a_int[i] = dataa[i] ^ 1;							int_dataa = (a_int + 1) * (-1) ;						end					else int_dataa = dataa ;					// convert signed datab					if(datab[lpm_widthb-1] == 1)						begin							int_datab = 0 ;							for(j = 0; j < lpm_widthb - 1; j = j + 1)								b_int[j] = datab[j] ^ 1;							int_datab = (b_int + 1) * (-1) ;						end					else int_datab = datab ;					// convert signed sum					if(sum[lpm_widths-1] == 1)						begin							int_sum = 0 ;							for(k = 0; k < lpm_widths - 1; k = k + 1)								s_int[k] = sum[k] ^ 1;							int_sum = (s_int + 1) * (-1) ;						end					else int_sum = sum ;				end			else 				begin					int_dataa = {lpm_widtha{1'bx}} ;					int_datab = {lpm_widthb{1'bx}} ;					int_sum   = {lpm_widths{1'bx}} ;				end		p_int = int_dataa * int_datab + int_sum ;		maxs_mn = ((lpm_widtha+lpm_widthb)>lpm_widths)?lpm_widtha+lpm_widthb:lpm_widths ;		if(lpm_widthp >= maxs_mn)			tmp_result = p_int ;		else			begin				p_reg = p_int;				for(m = 0; m < lpm_widthp; m = m +1)					tmp_result[lpm_widthp-1-m] = p_reg[maxs_mn-1-m] ;			end 	end	always @(posedge clock or posedge aclr)	begin	  if(aclr)		begin			for(p = 0; p <= lpm_pipeline; p = p + 1)				tmp_result2[p] = 'b0;		end	  else if (clken == 1)	  begin :syn_block		tmp_result2[lpm_pipeline] = tmp_result ;		for(n = 0; n < lpm_pipeline; n = n +1)		tmp_result2[n] = tmp_result2[n+1] ;	  end	end  assign result = (lpm_pipeline > 0) ? tmp_result2[0] : tmp_result ;endmodule // lpm_mult