////  Copyright (c) 2003 Launchbird Design Systems, Inc.//  All rights reserved.//  //  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met://    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.//  //  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.//  //  //  Overview://  //    Memory interleavers are often used in DSP for reordering continuous streaming data.//    The interleaver is comprised of two interleaving memories.  One memory loads and//    reorders data, while the other memory dumps the data to the output.//    Once loading and dumping of data are complete, the memories reverse roles.//    The dumping memory continuously cycles though the entire memory starting at address 0.//  //  Interface://  //    Synchronization://      clock_c  : Clock input.//  //    Inputs://      swap_i   : Swap signal to interleave memories.  Pulse occurs one frame before the switch//                 and may coincide with the last input data.//      write_i  : Write enable for input data.//      addr_i   : Address for input data.//      data_i   : Input data.//  //    Outputs://      sync_primary_o    : Output sync plus occurs one frame before data new dump.//      sync_secondary_o  : Secondary sync plus occurs one frame before data at address 0 is dumped.//      data_o            : Output data.//  //  Built In Parameters://  //    Address Width  = 7//    Data Width     = 32//  //  //  //  //  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com//  //  Build Date : Fri Aug 22 09:33:14 CDT 2003//  //  Interface//  //    Build Name    : cf_interleaver_7_32//    Clock Domains : clock_c  //    Vector Input  : swap_i(1)//    Vector Input  : write_i(1)//    Vector Input  : addr_i(7)//    Vector Input  : data_i(32)//    Vector Output : sync_primary_o(1)//    Vector Output : sync_secondary_o(1)//    Vector Output : data_o(32)//  //  //  #include <stdio.h>#include <stdlib.h>#include <time.h>#include "cf_interleaver_7_32.h"static unsigned char n84[1];static unsigned char *sync_primary_o;static unsigned char n79[4];static unsigned char n58[1];static unsigned char n28[1];static unsigned char n27[1];static unsigned char n26[1];static unsigned char n25[1];static unsigned char n22[1];static unsigned char n21[1];static unsigned char n20[1];static unsigned char n19[1];static unsigned char n18[1];static unsigned char n17[1];static unsigned char n16[1];static unsigned char n7[1];static unsigned char *data_i;static unsigned char *addr_i;static unsigned char *write_i;static unsigned char *swap_i;static unsigned char n2[1];static unsigned char n1[1];static unsigned char *data_o;static unsigned char n59[1];static unsigned char n57[1];static unsigned char n57r[1];static unsigned char n57e[1];static unsigned char n57d[1];static unsigned char n32[1];static unsigned char n10[1];static unsigned char *sync_secondary_o;static unsigned char n45[1];static unsigned char n44[1];static unsigned char n35[1];static unsigned char n34[1];static unsigned char n33[1];static unsigned char n15[1];static unsigned char n15r[1];static unsigned char n15e[1];static unsigned char n15d[1];static unsigned char n48[1];static unsigned char n36[1];static unsigned char n49[1];static unsigned char n37[1];static unsigned char n66[1];static unsigned char n50[1];static unsigned char n38[1];static unsigned char n78[1];static unsigned char n78r[1];static unsigned char n78e[1];static unsigned char n78d[1];static unsigned char n71[4];static unsigned char n71e[1];static unsigned char n71w[1];static unsigned char n71aw[1];static unsigned char n71ar[1];static unsigned char n71dw[4];static unsigned char n71m[512];static unsigned char n60[1];static unsigned char n43[1];static unsigned char n43r[1];static unsigned char n43e[1];static unsigned char n43d[1];static unsigned char n65[4];static unsigned char n65e[1];static unsigned char n65w[1];static unsigned char n65aw[1];static unsigned char n65ar[1];static unsigned char n65dw[4];static unsigned char n65m[512];void cf_interleaver_7_32_ports(unsigned char* port_swap_i, unsigned char* port_write_i, unsigned char* port_addr_i, unsigned char* port_data_i, unsigned char* port_sync_primary_o, unsigned char* port_sync_secondary_o, unsigned char* port_data_o) {  swap_i = port_swap_i;  write_i = port_write_i;  addr_i = port_addr_i;  data_i = port_data_i;  sync_primary_o = port_sync_primary_o;  sync_secondary_o = port_sync_secondary_o;  data_o = port_data_o;}void cf_interleaver_7_32_calc() {  n84[0] = 1;  sync_primary_o[0] = n57[0];  if (n78[0]) {    n79[0] = n71[0];    n79[1] = n71[1];    n79[2] = n71[2];    n79[3] = n71[3];  }  else {    n79[0] = n65[0];    n79[1] = n65[1];    n79[2] = n65[2];    n79[3] = n65[3];  }  n58[0] = 0;  n28[0] = 2;  n27[0] = 0;  n26[0] = 0;  n25[0] = 0;  n22[0] = 1;  n21[0] = 2;  n20[0] = 0;  n19[0] = 0;  n18[0] = 1;  n17[0] = 1;  n16[0] = 0;  n7[0] = 1;  n2[0] = 0;  n1[0] = 1;  data_o[0] = n79[0];  data_o[1] = n79[1];  data_o[2] = n79[2];  data_o[3] = n79[3];  n59[0] = n15[0] == n58[0] ? 1 : 0;  n57r[0] = n2[0];  n57e[0] = n1[0];  n57d[0] = swap_i[0];  n32[0] = 255 & (swap_i[0] << 1 | n43[0]);  { unsigned int tmp; (tmp = (unsigned int) n15[0] + (unsigned int) n7[0], n10[0] = 127 & (unsigned char) tmp); }  sync_secondary_o[0] = n59[0];  n45[0] = n32[0] == n28[0] ? 1 : 0;  n44[0] = n32[0] == n27[0] ? 1 : 0;  n35[0] = n32[0] == n22[0] ? 1 : 0;  n34[0] = n32[0] == n21[0] ? 1 : 0;  n33[0] = n32[0] == n20[0] ? 1 : 0;  n15r[0] = swap_i[0];  n15e[0] = n1[0];  n15d[0] = n10[0];  if (n45[0]) {    n48[0] = n25[0];  }  else {    n48[0] = n84[0];  }  if (n35[0]) {    n36[0] = n17[0];  }  else {    n36[0] = n16[0];  }  if (n44[0]) {    n49[0] = n26[0];  }  else {    n49[0] = n48[0];  }  if (n34[0]) {    n37[0] = n18[0];  }  else {    n37[0] = n36[0];  }  n66[0] = write_i[0] & n49[0];  n50[0] = 1 & ~n49[0];  if (n33[0]) {    n38[0] = n19[0];  }  else {    n38[0] = n37[0];  }  n78r[0] = n2[0];  n78e[0] = n1[0];  n78d[0] = n50[0];  n71e[0] = n1[0];  n71w[0] = n66[0];  n71aw[0] = addr_i[0];  n71ar[0] = n15[0];  n71dw[0] = data_i[0];  n71dw[1] = data_i[1];  n71dw[2] = data_i[2];  n71dw[3] = data_i[3];  n60[0] = write_i[0] & n50[0];  n43r[0] = n2[0];  n43e[0] = n1[0];  n43d[0] = n38[0];  n65e[0] = n1[0];  n65w[0] = n60[0];  n65aw[0] = addr_i[0];  n65ar[0] = n15[0];  n65dw[0] = data_i[0];  n65dw[1] = data_i[1];  n65dw[2] = data_i[2];  n65dw[3] = data_i[3];}void cf_interleaver_7_32_init() {  n84[0] = 0;  { int index; for (index = 4; index > 0;) n79[--index] = 0; }  n58[0] = 0;  n28[0] = 0;  n27[0] = 0;  n26[0] = 0;  n25[0] = 0;  n22[0] = 0;  n21[0] = 0;  n20[0] = 0;  n19[0] = 0;  n18[0] = 0;  n17[0] = 0;  n16[0] = 0;  n7[0] = 0;  n2[0] = 0;  n1[0] = 0;  n59[0] = 0;  n57[0] = 0;  n57r[0] = 0;  n57e[0] = 0;  n57d[0] = 0;  n32[0] = 0;  n10[0] = 0;  n45[0] = 0;  n44[0] = 0;  n35[0] = 0;