////  Copyright (c) 2003 Launchbird Design Systems, Inc.//  All rights reserved.//  //  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met://    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.//  //  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.//  //  //  Overview://  //    Memory interleavers are often used in DSP for reordering continuous streaming data.//    The interleaver is comprised of two interleaving memories.  One memory loads and//    reorders data, while the other memory dumps the data to the output.//    Once loading and dumping of data are complete, the memories reverse roles.//    The dumping memory continuously cycles though the entire memory starting at address 0.//  //  Interface://  //    Synchronization://      clock_c  : Clock input.//  //    Inputs://      swap_i   : Swap signal to interleave memories.  Pulse occurs one frame before the switch//                 and may coincide with the last input data.//      write_i  : Write enable for input data.//      addr_i   : Address for input data.//      data_i   : Input data.//  //    Outputs://      sync_primary_o    : Output sync plus occurs one frame before data new dump.//      sync_secondary_o  : Secondary sync plus occurs one frame before data at address 0 is dumped.//      data_o            : Output data.//  //  Built In Parameters://  //    Address Width  = 7//    Data Width     = 32//  //  //  //  //  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com//  //  Build Date : Fri Aug 22 09:33:14 CDT 2003//  //  Interface//  //    Build Name    : cf_interleaver_7_32//    Clock Domains : clock_c  //    Vector Input  : swap_i(1)//    Vector Input  : write_i(1)//    Vector Input  : addr_i(7)//    Vector Input  : data_i(32)//    Vector Output : sync_primary_o(1)//    Vector Output : sync_secondary_o(1)//    Vector Output : data_o(32)//  //  //  #ifdef __cplusplusextern "C" {#endifvoid cf_interleaver_7_32_ports(unsigned char* port_swap_i, unsigned char* port_write_i, unsigned char* port_addr_i, unsigned char* port_data_i, unsigned char* port_sync_primary_o, unsigned char* port_sync_secondary_o, unsigned char* port_data_o);void cf_interleaver_7_32_init();void cf_interleaver_7_32_calc();void cf_interleaver_7_32_cycle_clock();void cf_interleaver_7_32_sim_init(const char* file);void cf_interleaver_7_32_sim_end();void cf_interleaver_7_32_sim_sample();#ifdef __cplusplus}#endif