?? cf_interleaver_7_8.py
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## Copyright (c) 2003 Launchbird Design Systems, Inc.# All rights reserved.# # Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:# Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.# Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,# INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.# IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.# # # Overview:# # Memory interleavers are often used in DSP for reordering continuous streaming data.# The interleaver is comprised of two interleaving memories. One memory loads and# reorders data, while the other memory dumps the data to the output.# Once loading and dumping of data are complete, the memories reverse roles.# The dumping memory continuously cycles though the entire memory starting at address 0.# # Interface:# # Synchronization:# clock_c : Clock input.# # Inputs:# swap_i : Swap signal to interleave memories. Pulse occurs one frame before the switch# and may coincide with the last input data.# write_i : Write enable for input data.# addr_i : Address for input data.# data_i : Input data.# # Outputs:# sync_primary_o : Output sync plus occurs one frame before data new dump.# sync_secondary_o : Secondary sync plus occurs one frame before data at address 0 is dumped.# data_o : Output data.# # Built In Parameters:# # Address Width = 7# Data Width = 8# # # # # Generated by Confluence 0.6.3 -- Launchbird Design Systems, Inc. -- www.launchbird.com# # Build Date : Fri Aug 22 09:32:54 CDT 2003# # Interface# # Build Name : cf_interleaver_7_8# Clock Domains : clock_c # Vector Input : swap_i(1)# Vector Input : write_i(1)# Vector Input : addr_i(7)# Vector Input : data_i(8)# Vector Output : sync_primary_o(1)# Vector Output : sync_secondary_o(1)# Vector Output : data_o(8)# # # import sysimport timeclass cf_interleaver_7_8: def init(self): self.n84 = 0L self.n80 = 0L self.n79 = 0L self.n58 = 0L self.n28 = 0L self.n27 = 0L self.n26 = 0L self.n25 = 0L self.n22 = 0L self.n21 = 0L self.n20 = 0L self.n19 = 0L self.n18 = 0L self.n17 = 0L self.n16 = 0L self.n7 = 0L self.n6 = 0L self.n5 = 0L self.n4 = 0L self.n3 = 0L self.n2 = 0L self.n1 = 0L self.n82 = 0L self.n59 = 0L self.n57 = 0L self.n57r = 0L self.n57e = 0L self.n57d = 0L self.n32 = 0L self.n10 = 0L self.n81 = 0L self.n45 = 0L self.n44 = 0L self.n35 = 0L self.n34 = 0L self.n33 = 0L self.n15 = 0L self.n15r = 0L self.n15e = 0L self.n15d = 0L self.n48 = 0L self.n36 = 0L self.n49 = 0L self.n37 = 0L self.n66 = 0L self.n50 = 0L self.n38 = 0L self.n78 = 0L self.n78r = 0L self.n78e = 0L self.n78d = 0L self.n71 = 0L self.n71e = 0L self.n71w = 0L self.n71aw = 0L self.n71ar = 0L self.n71dw = 0L self.n71m = [0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,] self.n60 = 0L self.n43 = 0L self.n43r = 0L self.n43e = 0L self.n43d = 0L self.n65 = 0L self.n65e = 0L self.n65w = 0L self.n65aw = 0L self.n65ar = 0L self.n65dw = 0L self.n65m = [0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,0L,] self.calc(0L, 0L, 0L, 0L, ) def calc(self, swap_i, write_i, addr_i, data_i, ): self.n84 = 0x1L sync_primary_o = self.n57 self.n80 = self.n57 if self.n78: self.n79 = self.n71 else: self.n79 = self.n65 self.n58 = 0x00L self.n28 = 0x2L self.n27 = 0x0L self.n26 = 0x0L self.n25 = 0x0L self.n22 = 0x1L self.n21 = 0x2L self.n20 = 0x0L self.n19 = 0x0L self.n18 = 0x1L self.n17 = 0x1L self.n16 = 0x0L self.n7 = 0x01L self.n6 = data_i self.n5 = addr_i self.n4 = write_i self.n3 = swap_i self.n2 = 0x0L self.n1 = 0x1L data_o = self.n79 self.n82 = self.n79 if self.n15 == self.n58: self.n59 = 1L else: self.n59 = 0L self.n57r = self.n2 self.n57e = self.n1 self.n57d = self.n3 self.n32 = self.n3 << 1 | self.n43 self.n10 = (self.n15 + self.n7) & 0x7FL sync_secondary_o = self.n59 self.n81 = self.n59 if self.n32 == self.n28: self.n45 = 1L else: self.n45 = 0L if self.n32 == self.n27: self.n44 = 1L else: self.n44 = 0L if self.n32 == self.n22: self.n35 = 1L else: self.n35 = 0L if self.n32 == self.n21: self.n34 = 1L else: self.n34 = 0L if self.n32 == self.n20: self.n33 = 1L else: self.n33 = 0L self.n15r = self.n3 self.n15e = self.n1 self.n15d = self.n10 if self.n45: self.n48 = self.n25 else: self.n48 = self.n84 if self.n35: self.n36 = self.n17 else: self.n36 = self.n16 if self.n44: self.n49 = self.n26 else: self.n49 = self.n48 if self.n34: self.n37 = self.n18 else: self.n37 = self.n36 self.n66 = self.n4 & self.n49 self.n50 = ~self.n49 & 0x1L if self.n33: self.n38 = self.n19 else: self.n38 = self.n37 self.n78r = self.n2 self.n78e = self.n1 self.n78d = self.n50 self.n71e = self.n1 self.n71w = self.n66 self.n71aw = self.n5 self.n71ar = self.n15 self.n71dw = self.n6 self.n60 = self.n4 & self.n50 self.n43r = self.n2 self.n43e = self.n1 self.n43d = self.n38 self.n65e = self.n1 self.n65w = self.n60 self.n65aw = self.n5 self.n65ar = self.n15 self.n65dw = self.n6 return (sync_primary_o, sync_secondary_o, data_o, ) def cycle_clock(self): if self.n15r: self.n15 = 0L elif self.n15e: self.n15 = self.n15d if self.n43r: self.n43 = 0L elif self.n43e: self.n43 = self.n43d if self.n57r: self.n57 = 0L elif self.n57e: self.n57 = self.n57d if self.n65e: if self.n65w: self.n65m[self.n65aw] = self.n65dw self.n65 = self.n65m[self.n65ar] if self.n71e: if self.n71w: self.n71m[self.n71aw] = self.n71dw self.n71 = self.n71m[self.n71ar] if self.n78r: self.n78 = 0L elif self.n78e: self.n78 = self.n78d def sim_init(self, vcdFile): self.sim_file = open(vcdFile, 'w') self.sim_count = 1 self.init() self.sim_n3 = self.n3 self.sim_n4 = self.n4 self.sim_n5 = self.n5 self.sim_n6 = self.n6 self.sim_n80 = self.n80 self.sim_n81 = self.n81 self.sim_n82 = self.n82 self.sim_file.write("$date\n") self.sim_file.write(" " + time.strftime("%a %b %d %H:%M:%S %Y", time.localtime()) + "\n") self.sim_file.write("$end\n") self.sim_file.write("$version\n Confluence 0.6.3 -- Launchbird Design Systems, Inc.\n$end\n") self.sim_file.write("$timescale\n 1 ns\n$end\n") self.sim_file.write("$scope module cf_interleaver_7_8 $end\n") self.sim_file.write("$var wire 1 ! swap_i $end\n") self.sim_file.write("$var wire 1 \" write_i $end\n") self.sim_file.write("$var wire 7 # addr_i $end\n") self.sim_file.write("$var wire 8 $ data_i $end\n") self.sim_file.write("$var wire 1 % sync_primary_o $end\n") self.sim_file.write("$var wire 1 & sync_secondary_o $end\n") self.sim_file.write("$var wire 8 ' data_o $end\n") self.sim_file.write("$upscope $end\n") self.sim_file.write("$enddefinitions $end\n") self.sim_file.write("#0\n") self.sim_file.write("$dumpvars\n") if self.n3: self.sim_file.write("1!\n") else: self.sim_file.write("0!\n") if self.n4: self.sim_file.write("1\"\n") else: self.sim_file.write("0\"\n") found = 0 for bit in range(6, -1, -1): if found: if self.n5 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n5 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" #\n") found = 0 for bit in range(7, -1, -1): if found: if self.n6 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n6 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" $\n") if self.n80: self.sim_file.write("1%\n") else: self.sim_file.write("0%\n") if self.n81: self.sim_file.write("1&\n") else: self.sim_file.write("0&\n") found = 0 for bit in range(7, -1, -1): if found: if self.n82 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n82 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" '\n") self.sim_file.write("$end\n") def sim_end(self): self.sim_file.write("#%d\n" % self.sim_count) self.sim_file.close() def sim_sample(self): changed = 0 if self.sim_n3 != self.n3: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) if self.n3: self.sim_file.write("1!\n") else: self.sim_file.write("0!\n") self.sim_n3 = self.n3 if self.sim_n4 != self.n4: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) if self.n4: self.sim_file.write("1\"\n") else: self.sim_file.write("0\"\n") self.sim_n4 = self.n4 if self.sim_n5 != self.n5: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) found = 0 for bit in range(6, -1, -1): if found: if self.n5 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n5 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" #\n") self.sim_n5 = self.n5 if self.sim_n6 != self.n6: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) found = 0 for bit in range(7, -1, -1): if found: if self.n6 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n6 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" $\n") self.sim_n6 = self.n6 if self.sim_n80 != self.n80: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) if self.n80: self.sim_file.write("1%\n") else: self.sim_file.write("0%\n") self.sim_n80 = self.n80 if self.sim_n81 != self.n81: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) if self.n81: self.sim_file.write("1&\n") else: self.sim_file.write("0&\n") self.sim_n81 = self.n81 if self.sim_n82 != self.n82: if not changed: changed = 1 self.sim_file.write("#%d\n" % self.sim_count) found = 0 for bit in range(7, -1, -1): if found: if self.n82 & (2L ** bit): self.sim_file.write("1") else: self.sim_file.write("0") else: if self.n82 & (2L ** bit): self.sim_file.write("b1") found = 1 if not found: self.sim_file.write("b0") self.sim_file.write(" '\n") self.sim_n82 = self.n82 self.sim_count = self.sim_count + 1?? 快捷鍵說明
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