?? speaker.txt
字號:
Library ieee;
Use ieee.std_logic_1164.all;
Entity speaker is
Port(
clk : in std_logic;
Freq_num : in integer range 0 to 2047; --16#7FF#
speaker : out std_logic);
End speaker;
Architecture a1 of speaker is
signal power_speaker : std_logic;
begin
Process(clk)
variable count11bit: integer range 0 to 2047;
Begin
if clk'event and clk='1' then
if count11bit=2047 then
count11bit:=Freq_num;
power_speaker<='1';
Else
count11bit:=count11bit+1;
power_speaker<='0';
end if;
end if;
end process;
--將輸出再進(jìn)行2分頻,將脈沖展寬,以使揚(yáng)聲器有足夠功率發(fā)音
process(power_speaker)
variable count2bit: std_logic;
Begin
if power_speaker'event and power_speaker='1' then
count2bit:=not count2bit;
if count2bit='1' then
speaker<='1';
else speaker<='0';
end if;
end if;
end process;
End a1;
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