?? mod6_divide.tan.rpt
字號:
Timing Analyzer report for mod6_divide
Thu Nov 02 14:01:02 2006
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tco
7. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 6.468 ns ; clk_divide~reg0 ; clk_divide ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; clk_divide~reg0 ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------+-----------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+--------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; clk_divide~reg0 ; clk ; clk ; None ; None ; 0.987 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[2] ; clk ; clk ; None ; None ; 0.984 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[1] ; clk ; clk ; None ; None ; 0.982 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[1] ; clk ; clk ; None ; None ; 0.735 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; clk_divide~reg0 ; clk ; clk ; None ; None ; 0.734 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[2] ; cnt[2] ; clk ; clk ; None ; None ; 0.734 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; clk_divide~reg0 ; clk ; clk ; None ; None ; 0.656 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[2] ; clk ; clk ; None ; None ; 0.655 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[0] ; cnt[0] ; clk ; clk ; None ; None ; 0.653 ns ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; cnt[1] ; cnt[1] ; clk ; clk ; None ; None ; 0.648 ns ;
+-------+------------------------------------------------+--------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------+------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------+------------+------------+
; N/A ; None ; 6.468 ns ; clk_divide~reg0 ; clk_divide ; clk ;
+-------+--------------+------------+-----------------+------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Thu Nov 02 14:01:02 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off mod6_divide -c mod6_divide --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "cnt[0]" and destination register "clk_divide~reg0"
Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 0.987 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y9_N4; Fanout = 4; REG Node = 'cnt[0]'
Info: 2: + IC(0.448 ns) + CELL(0.539 ns) = 0.987 ns; Loc. = LC_X52_Y9_N5; Fanout = 1; REG Node = 'clk_divide~reg0'
Info: Total cell delay = 0.539 ns ( 54.61 % )
Info: Total interconnect delay = 0.448 ns ( 45.39 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 2.974 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(1.604 ns) + CELL(0.542 ns) = 2.974 ns; Loc. = LC_X52_Y9_N5; Fanout = 1; REG Node = 'clk_divide~reg0'
Info: Total cell delay = 1.370 ns ( 46.07 % )
Info: Total interconnect delay = 1.604 ns ( 53.93 % )
Info: - Longest clock path from clock "clk" to source register is 2.974 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(1.604 ns) + CELL(0.542 ns) = 2.974 ns; Loc. = LC_X52_Y9_N4; Fanout = 4; REG Node = 'cnt[0]'
Info: Total cell delay = 1.370 ns ( 46.07 % )
Info: Total interconnect delay = 1.604 ns ( 53.93 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "clk_divide" through register "clk_divide~reg0" is 6.468 ns
Info: + Longest clock path from clock "clk" to source register is 2.974 ns
Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
Info: 2: + IC(1.604 ns) + CELL(0.542 ns) = 2.974 ns; Loc. = LC_X52_Y9_N5; Fanout = 1; REG Node = 'clk_divide~reg0'
Info: Total cell delay = 1.370 ns ( 46.07 % )
Info: Total interconnect delay = 1.604 ns ( 53.93 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.338 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y9_N5; Fanout = 1; REG Node = 'clk_divide~reg0'
Info: 2: + IC(0.962 ns) + CELL(2.376 ns) = 3.338 ns; Loc. = PIN_T2; Fanout = 0; PIN Node = 'clk_divide'
Info: Total cell delay = 2.376 ns ( 71.18 % )
Info: Total interconnect delay = 0.962 ns ( 28.82 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Thu Nov 02 14:01:02 2006
Info: Elapsed time: 00:00:00
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