library verilog;use verilog.vl_types.all;entity blocking is    port(        clk             : in     vl_logic;        a               : in     vl_logic_vector(3 downto 0);        b               : out    vl_logic_vector(3 downto 0);        c               : out    vl_logic_vector(3 downto 0);        d               : out    vl_logic_vector(3 downto 0);        e               : out    vl_logic_vector(3 downto 0)    );end blocking;