?? clock.vho
字號(hào):
\Mux1~127_I_pathsel\ <= "00000001111";
\Mux2~140_I_modesel\ <= "1001001010101";
\Mux2~140_I_pathsel\ <= "00000001111";
\Mux2~141_I_modesel\ <= "1001001010101";
\Mux2~141_I_pathsel\ <= "00000001111";
\Mux2~142_I_modesel\ <= "1001001010101";
\Mux2~142_I_pathsel\ <= "00000000111";
\Mux2~143_I_modesel\ <= "1001001010101";
\Mux2~143_I_pathsel\ <= "00000001111";
\Mux11~30_I_modesel\ <= "1001001010101";
\Mux11~30_I_pathsel\ <= "00000001111";
\Mux10~29_I_modesel\ <= "1001001010101";
\Mux10~29_I_pathsel\ <= "00000001111";
\Mux9~77_I_modesel\ <= "1001001010101";
\Mux9~77_I_pathsel\ <= "00000001110";
\Mux8~31_I_modesel\ <= "1001001010101";
\Mux8~31_I_pathsel\ <= "00000001111";
\Mux7~49_I_modesel\ <= "1001001010101";
\Mux7~49_I_pathsel\ <= "00000001110";
\Mux6~128_I_modesel\ <= "1001001010101";
\Mux6~128_I_pathsel\ <= "00000001110";
\Mux5~33_I_modesel\ <= "1001001010101";
\Mux5~33_I_pathsel\ <= "00000001111";
\LEDOUT[0]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[1]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[2]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[3]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[4]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[5]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[6]~I_modesel\ <= "000000000000000000000000010";
\LEDOUT[7]~I_modesel\ <= "000000000000000000000000010";
\sel[0]~I_modesel\ <= "000000000000000000000000010";
\sel[1]~I_modesel\ <= "000000000000000000000000010";
\sel[2]~I_modesel\ <= "000000000000000000000000010";
\INV_INST_Mux10~29\ : INV
PORT MAP (
IN1 => \Mux10~29\,
Y => \ALT_INV_Mux10~29\);
\INV_INST_Mux9~77\ : INV
PORT MAP (
IN1 => \Mux9~77\,
Y => \ALT_INV_Mux9~77\);
\INV_INST_Mux8~31\ : INV
PORT MAP (
IN1 => \Mux8~31\,
Y => \ALT_INV_Mux8~31\);
\INV_INST_Mux7~49\ : INV
PORT MAP (
IN1 => \Mux7~49\,
Y => \ALT_INV_Mux7~49\);
\INV_INST_Mux5~33\ : INV
PORT MAP (
IN1 => \Mux5~33\,
Y => \ALT_INV_Mux5~33\);
\INV_INST_reset~combout\ : INV
PORT MAP (
IN1 => \reset~combout\,
Y => \ALT_INV_reset~combout\);
lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
IN1 => GND,
Y => lcell_ff_enable_asynch_arcs_out);
-- atom is at PIN_17
\clk~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
-- input_async_reset => "none",
-- input_power_up => "low",
-- input_register_mode => "none",
-- input_sync_reset => "none",
-- oe_async_reset => "none",
-- oe_power_up => "low",
-- oe_register_mode => "none",
-- oe_sync_reset => "none",
-- operation_mode => "input",
-- output_async_reset => "none",
-- output_power_up => "low",
-- output_register_mode => "none",
-- output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
datain => GND,
oe => GND,
outclk => GND,
outclkena => VCC,
inclk => GND,
inclkena => VCC,
areset => GND,
sreset => GND,
modesel => \clk~I_modesel\,
combout => \clk~combout\,
padio => ww_clk);
-- atom is at LC_X16_Y7_N0
\clk_counter_1h~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_1h = DFFEAS(\Equal6~38\ & (\clk_10m[0]\ & (\clk_10m[2]\) # !\clk_10m[0]\ & clk_counter_1h) # !\Equal6~38\ & clk_counter_1h, GLOBAL(clk_counter_10m), VCC, , \reset~combout\, , , , )
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "E4CC",
-- operation_mode => "normal",
-- output_mode => "reg_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \clk_counter_1h~I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => clk_counter_10m,
dataa => \Equal6~38\,
datab => clk_counter_1h,
datac => \clk_10m[2]\,
datad => \clk_10m[0]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => \reset~combout\,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \clk_counter_1h~I_modesel\,
regout => clk_counter_1h);
-- atom is at LC_X24_Y9_N4
\clk_counter_10s~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10s = DFFEAS(\Equal0~38\ & (\clk_1s[0]\ & \clk_1s[3]\ # !\clk_1s[0]\ & (clk_counter_10s)) # !\Equal0~38\ & (clk_counter_10s), GLOBAL(\clk~combout\), VCC, , \reset~combout\, , , , )
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "B8F0",
-- operation_mode => "normal",
-- output_mode => "reg_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \clk_counter_10s~I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => \clk~combout\,
dataa => \clk_1s[3]\,
datab => \Equal0~38\,
datac => clk_counter_10s,
datad => \clk_1s[0]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => \reset~combout\,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \clk_counter_10s~I_modesel\,
regout => clk_counter_10s);
-- atom is at LC_X26_Y13_N6
\clk_counter_10h~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10h = DFFEAS(\clk_1h[1]~216\ # clk_counter_10h & (\clk_1h[1]\ # !\process4~39\), GLOBAL(clk_counter_1h), VCC, , \reset~combout\, , , , )
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "FF8A",
-- operation_mode => "normal",
-- output_mode => "reg_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \clk_counter_10h~I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => clk_counter_1h,
dataa => clk_counter_10h,
datab => \clk_1h[1]\,
datac => \process4~39\,
datad => \clk_1h[1]~216\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => \reset~combout\,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \clk_counter_10h~I_modesel\,
regout => clk_counter_10h);
-- atom is at LC_X25_Y6_N2
\clk_counter_10m~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_10m = DFFEAS(\Equal4~38\ & (\clk_1m[0]\ & \clk_1m[3]\ # !\clk_1m[0]\ & (clk_counter_10m)) # !\Equal4~38\ & (clk_counter_10m), GLOBAL(clk_counter_1m), VCC, , \reset~combout\, , , , )
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "B8F0",
-- operation_mode => "normal",
-- output_mode => "reg_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \clk_counter_10m~I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => clk_counter_1m,
dataa => \clk_1m[3]\,
datab => \Equal4~38\,
datac => clk_counter_10m,
datad => \clk_1m[0]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => \reset~combout\,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \clk_counter_10m~I_modesel\,
regout => clk_counter_10m);
-- atom is at LC_X26_Y6_N4
\clk_counter_1m~I\ : cyclone_lcell
-- Equation(s):
-- clk_counter_1m = DFFEAS(\clk_10s[0]\ & (\Equal2~38\ & (\clk_10s[2]\) # !\Equal2~38\ & clk_counter_1m) # !\clk_10s[0]\ & (clk_counter_1m), GLOBAL(clk_counter_10s), VCC, , \reset~combout\, , , , )
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "F870",
-- operation_mode => "normal",
-- output_mode => "reg_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \clk_counter_1m~I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => clk_counter_10s,
dataa => \clk_10s[0]\,
datab => \Equal2~38\,
datac => clk_counter_1m,
datad => \clk_10s[2]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => \reset~combout\,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \clk_counter_1m~I_modesel\,
regout => clk_counter_1m);
-- atom is at LC_X26_Y13_N2
\process4~39_I\ : cyclone_lcell
-- Equation(s):
-- \process4~39\ = \clk_1h[0]\ & !\clk_1h[3]\ & (!\clk_1h[2]\)
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "0022",
-- operation_mode => "normal",
-- output_mode => "comb_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \process4~39_I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => GND,
dataa => \clk_1h[0]\,
datab => \clk_1h[3]\,
datac => VCC,
datad => \clk_1h[2]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => VCC,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \process4~39_I_modesel\,
combout => \process4~39\);
-- atom is at LC_X16_Y7_N7
\Equal6~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal6~38\ = !\clk_10m[1]\ & !\clk_10m[3]\
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "000F",
-- operation_mode => "normal",
-- output_mode => "comb_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \Equal6~38_I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => GND,
dataa => VCC,
datab => VCC,
datac => \clk_10m[1]\,
datad => \clk_10m[3]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => VCC,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \Equal6~38_I_modesel\,
combout => \Equal6~38\);
-- atom is at LC_X24_Y9_N5
\Equal0~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal0~38\ = !\clk_1s[2]\ & !\clk_1s[1]\
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "000F",
-- operation_mode => "normal",
-- output_mode => "comb_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \Equal0~38_I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => GND,
dataa => VCC,
datab => VCC,
datac => \clk_1s[2]\,
datad => \clk_1s[1]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => VCC,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \Equal0~38_I_modesel\,
combout => \Equal0~38\);
-- atom is at LC_X25_Y6_N8
\Equal4~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal4~38\ = !\clk_1m[1]\ & !\clk_1m[2]\
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "000F",
-- operation_mode => "normal",
-- output_mode => "comb_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \Equal4~38_I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => GND,
dataa => VCC,
datab => VCC,
datac => \clk_1m[1]\,
datad => \clk_1m[2]\,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
ena => VCC,
cin => GND,
cin0 => GND,
cin1 => VCC,
inverta => GND,
regcascin => GND,
modesel => \Equal4~38_I_modesel\,
combout => \Equal4~38\);
-- atom is at LC_X26_Y6_N5
\Equal2~38_I\ : cyclone_lcell
-- Equation(s):
-- \Equal2~38\ = !\clk_10s[1]\ & !\clk_10s[3]\
-- pragma translate_off
-- GENERIC MAP (
-- lut_mask => "0303",
-- operation_mode => "normal",
-- output_mode => "comb_only",
-- register_cascade_mode => "off",
-- sum_lutc_input => "datac",
-- synch_mode => "off")
-- pragma translate_on
PORT MAP (
pathsel => \Equal2~38_I_pathsel\,
enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
clk => GND,
dataa => VCC,
datab => \clk_10s[1]\,
datac => \clk_10s[3]\,
datad => VCC,
aclr => GND,
aload => GND,
sclr => GND,
sload => GND,
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