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?? clock.vho

?? 基于SMART-I實驗平臺的時鐘電路設計與實現
?? VHO
?? 第 1 頁 / 共 5 頁
字號: 
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Equal2~38_I_modesel\,
	combout => \Equal2~38\);

-- atom is at LC_X18_Y11_N3
\sel_temp[0]~I\ : cyclone_lcell
-- Equation(s):
-- \sel_temp[0]\ = DFFEAS(!\sel_temp[0]\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "00FF",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \sel_temp[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => \sel_temp[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \sel_temp[0]~I_modesel\,
	regout => \sel_temp[0]\);

-- atom is at LC_X18_Y11_N8
\sel_temp[1]~I\ : cyclone_lcell
-- Equation(s):
-- \sel_temp[1]\ = DFFEAS(\sel_temp[1]\ $ \sel_temp[0]\, GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0FF0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \sel_temp[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => VCC,
	datac => \sel_temp[1]\,
	datad => \sel_temp[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \sel_temp[1]~I_modesel\,
	regout => \sel_temp[1]\);

-- atom is at LC_X18_Y11_N4
\sel_temp[2]~I\ : cyclone_lcell
-- Equation(s):
-- \sel_temp[2]\ = DFFEAS(\sel_temp[2]\ $ (\sel_temp[1]\ & \sel_temp[0]\), GLOBAL(\clk~combout\), VCC, , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "3CF0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \sel_temp[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => \sel_temp[1]\,
	datac => \sel_temp[2]\,
	datad => \sel_temp[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \sel_temp[2]~I_modesel\,
	regout => \sel_temp[2]\);

-- atom is at LC_X18_Y11_N1
\Mux4~24_I\ : cyclone_lcell
-- Equation(s):
-- \Mux4~24\ = !\sel_temp[0]\ & (\sel_temp[1]\ $ \sel_temp[2]\)

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "003C",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux4~24_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => VCC,
	datab => \sel_temp[1]\,
	datac => \sel_temp[2]\,
	datad => \sel_temp[0]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux4~24_I_modesel\,
	combout => \Mux4~24\);

-- atom is at PIN_16
\reset~I\ : cyclone_io
-- pragma translate_off
-- GENERIC MAP (
--	input_async_reset => "none",
--	input_power_up => "low",
--	input_register_mode => "none",
--	input_sync_reset => "none",
--	oe_async_reset => "none",
--	oe_power_up => "low",
--	oe_register_mode => "none",
--	oe_sync_reset => "none",
--	operation_mode => "input",
--	output_async_reset => "none",
--	output_power_up => "low",
--	output_register_mode => "none",
--	output_sync_reset => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	oe => GND,
	outclk => GND,
	outclkena => VCC,
	inclk => GND,
	inclkena => VCC,
	areset => GND,
	sreset => GND,
	modesel => \reset~I_modesel\,
	combout => \reset~combout\,
	padio => ww_reset);

-- atom is at LC_X26_Y6_N9
\clk_10s[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10s[0]\ = DFFEAS(!\clk_10s[0]\, GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0F0F",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10s[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10s,
	dataa => VCC,
	datab => VCC,
	datac => \clk_10s[0]\,
	datad => VCC,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10s[0]~I_modesel\,
	regout => \clk_10s[0]\);

-- atom is at LC_X26_Y6_N6
\clk_10s[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10s[2]\ = DFFEAS(\clk_10s[0]\ & (\clk_10s[1]\ & (!\clk_10s[2]\) # !\clk_10s[1]\ & \clk_10s[3]\ & \clk_10s[2]\) # !\clk_10s[0]\ & (\clk_10s[2]\), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "7588",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10s[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10s,
	dataa => \clk_10s[0]\,
	datab => \clk_10s[1]\,
	datac => \clk_10s[3]\,
	datad => \clk_10s[2]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10s[2]~I_modesel\,
	regout => \clk_10s[2]\);

-- atom is at LC_X26_Y6_N8
\clk_10s[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10s[1]\ = DFFEAS(\clk_10s[0]\ & !\clk_10s[1]\ & (\clk_10s[3]\ # !\clk_10s[2]\) # !\clk_10s[0]\ & \clk_10s[1]\, GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "6466",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10s[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10s,
	dataa => \clk_10s[0]\,
	datab => \clk_10s[1]\,
	datac => \clk_10s[3]\,
	datad => \clk_10s[2]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10s[1]~I_modesel\,
	regout => \clk_10s[1]\);

-- atom is at LC_X26_Y6_N2
\clk_10s[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10s[3]\ = DFFEAS(\clk_10s[3]\ $ (\clk_10s[0]\ & \clk_10s[1]\ & \clk_10s[2]\), GLOBAL(clk_counter_10s), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "78F0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10s[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10s,
	dataa => \clk_10s[0]\,
	datab => \clk_10s[1]\,
	datac => \clk_10s[3]\,
	datad => \clk_10s[2]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10s[3]~I_modesel\,
	regout => \clk_10s[3]\);

-- atom is at LC_X24_Y9_N3
\clk_1s[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1s[0]\ = DFFEAS(!\clk_1s[0]\, GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "00FF",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1s[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => \clk_1s[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1s[0]~I_modesel\,
	regout => \clk_1s[0]\);

-- atom is at LC_X24_Y9_N9
\clk_1s[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1s[2]\ = DFFEAS(\clk_1s[2]\ $ (\clk_1s[1]\ & \clk_1s[0]\), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "3CF0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1s[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => VCC,
	datab => \clk_1s[1]\,
	datac => \clk_1s[2]\,
	datad => \clk_1s[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1s[2]~I_modesel\,
	regout => \clk_1s[2]\);

-- atom is at LC_X24_Y9_N0
\clk_1s[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1s[1]\ = DFFEAS(\clk_1s[1]\ & (!\clk_1s[0]\) # !\clk_1s[1]\ & \clk_1s[0]\ & (\clk_1s[2]\ # !\clk_1s[3]\), GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "31CC",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1s[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clk~combout\,
	dataa => \clk_1s[3]\,
	datab => \clk_1s[1]\,
	datac => \clk_1s[2]\,
	datad => \clk_1s[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1s[1]~I_modesel\,
	regout => \clk_1s[1]\);

-- atom is at LC_X24_Y9_N7
\clk_1s[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1s[3]\ = DFFEAS(\clk_1s[3]\ & (\clk_1s[1]\ $ \clk_1s[2]\ # !\clk_1s[0]\) # !\clk_1s[3]\ & \clk_1s[1]\ & \clk_1s[2]\ & \clk_1s[0]\, GLOBAL(\clk~combout\), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "68AA",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1s[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,

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亚洲欧美第一页_禁久久精品乱码_粉嫩av一区二区三区免费野_久草精品视频
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