?? clock.vho

?? 基于SMART-I實驗平臺的時鐘電路設計與實現
?? VHO
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-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0078",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1h[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1h,
	dataa => \clk_1h[2]\,
	datab => \Add4~103\,
	datac => \clk_1h[3]\,
	datad => \clk_1h[1]~216\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1h[3]~I_modesel\,
	regout => \clk_1h[3]\);

-- atom is at LC_X24_Y9_N6
\Mux0~123_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~123\ = \Mux0~122\ & (\clk_10h[3]\ # !\sel_temp[2]\) # !\Mux0~122\ & \sel_temp[2]\ & \clk_1h[3]\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "EA62",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux0~123_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \Mux0~122\,
	datab => \sel_temp[2]\,
	datac => \clk_1h[3]\,
	datad => \clk_10h[3]\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux0~123_I_modesel\,
	combout => \Mux0~123\);

-- atom is at LC_X25_Y6_N3
\clk_1m[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1m[0]\ = DFFEAS(!\clk_1m[0]\, GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "00FF",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1m[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1m,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => \clk_1m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1m[0]~I_modesel\,
	regout => \clk_1m[0]\);

-- atom is at LC_X25_Y6_N9
\clk_1m[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1m[1]\ = DFFEAS(\clk_1m[1]\ & (!\clk_1m[0]\) # !\clk_1m[1]\ & \clk_1m[0]\ & (\clk_1m[2]\ # !\clk_1m[3]\), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "0DF0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1m[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1m,
	dataa => \clk_1m[3]\,
	datab => \clk_1m[2]\,
	datac => \clk_1m[1]\,
	datad => \clk_1m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1m[1]~I_modesel\,
	regout => \clk_1m[1]\);

-- atom is at LC_X25_Y6_N5
\clk_1m[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1m[2]\ = DFFEAS(\clk_1m[2]\ $ (\clk_1m[1]\ & \clk_1m[0]\), GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "3CCC",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1m[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1m,
	dataa => VCC,
	datab => \clk_1m[2]\,
	datac => \clk_1m[1]\,
	datad => \clk_1m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1m[2]~I_modesel\,
	regout => \clk_1m[2]\);

-- atom is at LC_X25_Y6_N6
\clk_1m[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_1m[3]\ = DFFEAS(\clk_1m[3]\ & (\clk_1m[2]\ $ \clk_1m[1]\ # !\clk_1m[0]\) # !\clk_1m[3]\ & \clk_1m[2]\ & \clk_1m[1]\ & \clk_1m[0]\, GLOBAL(clk_counter_1m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "68AA",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_1m[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_1m,
	dataa => \clk_1m[3]\,
	datab => \clk_1m[2]\,
	datac => \clk_1m[1]\,
	datad => \clk_1m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_1m[3]~I_modesel\,
	regout => \clk_1m[3]\);

-- atom is at LC_X16_Y7_N3
\clk_10m[0]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10m[0]\ = DFFEAS(!\clk_10m[0]\, GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "00FF",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10m[0]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10m,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => \clk_10m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10m[0]~I_modesel\,
	regout => \clk_10m[0]\);

-- atom is at LC_X16_Y7_N8
\clk_10m[2]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10m[2]\ = DFFEAS(\clk_10m[1]\ & (\clk_10m[2]\ $ \clk_10m[0]\) # !\clk_10m[1]\ & \clk_10m[2]\ & (\clk_10m[3]\ # !\clk_10m[0]\), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "4AF0",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10m[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10m,
	dataa => \clk_10m[1]\,
	datab => \clk_10m[3]\,
	datac => \clk_10m[2]\,
	datad => \clk_10m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10m[2]~I_modesel\,
	regout => \clk_10m[2]\);

-- atom is at LC_X16_Y7_N9
\clk_10m[1]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10m[1]\ = DFFEAS(\clk_10m[1]\ & (!\clk_10m[0]\) # !\clk_10m[1]\ & \clk_10m[0]\ & (\clk_10m[3]\ # !\clk_10m[2]\), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "45AA",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10m[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10m,
	dataa => \clk_10m[1]\,
	datab => \clk_10m[3]\,
	datac => \clk_10m[2]\,
	datad => \clk_10m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10m[1]~I_modesel\,
	regout => \clk_10m[1]\);

-- atom is at LC_X16_Y7_N5
\clk_10m[3]~I\ : cyclone_lcell
-- Equation(s):
-- \clk_10m[3]\ = DFFEAS(\clk_10m[3]\ $ (\clk_10m[1]\ & \clk_10m[2]\ & \clk_10m[0]\), GLOBAL(clk_counter_10m), GLOBAL(\reset~combout\), , , , , , )

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "6CCC",
--	operation_mode => "normal",
--	output_mode => "reg_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \clk_10m[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => clk_counter_10m,
	dataa => \clk_10m[1]\,
	datab => \clk_10m[3]\,
	datac => \clk_10m[2]\,
	datad => \clk_10m[0]\,
	aclr => \ALT_INV_reset~combout\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \clk_10m[3]~I_modesel\,
	regout => \clk_10m[3]\);

-- atom is at LC_X16_Y7_N1
\Mux0~124_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~124\ = \sel_temp[0]\ & (\clk_10m[3]\) # !\sel_temp[0]\ & \clk_1m[3]\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "CACA",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux0~124_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_1m[3]\,
	datab => \clk_10m[3]\,
	datac => \sel_temp[0]\,
	datad => VCC,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux0~124_I_modesel\,
	combout => \Mux0~124\);

-- atom is at LC_X16_Y7_N6
\Mux0~125_I\ : cyclone_lcell
-- Equation(s):
-- \Mux0~125\ = \sel_temp[1]\ & (!\sel_temp[2]\ & \Mux0~124\) # !\sel_temp[1]\ & \Mux0~123\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "3A0A",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux0~125_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \Mux0~123\,
	datab => \sel_temp[2]\,
	datac => \sel_temp[1]\,
	datad => \Mux0~124\,
	aclr => GND,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \Mux0~125_I_modesel\,
	combout => \Mux0~125\);

-- atom is at LC_X16_Y7_N2
\Mux3~150_I\ : cyclone_lcell
-- Equation(s):
-- \Mux3~150\ = \sel_temp[0]\ & (\clk_10m[0]\) # !\sel_temp[0]\ & \clk_1m[0]\

-- pragma translate_off
-- GENERIC MAP (
--	lut_mask => "CACA",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	register_cascade_mode => "off",
--	sum_lutc_input => "datac",
--	synch_mode => "off")
-- pragma translate_on
PORT MAP (
	pathsel => \Mux3~150_I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => GND,
	dataa => \clk_1m[0]\,
	datab => \clk_10m[0]\,
	datac => \sel_temp[0]\,
	datad => VCC,
	aclr => GND,
	aloa
上一頁 1 2 3 45
?? 文件大小 302 K
?? 上傳用戶 x184372250
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關標簽

#SMART-I #實驗 #時鐘 #電路設計
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?? clock.vho

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