`include"./shuru.v"
`include"./counter.v"
`include"./dizhi.v"
`include"./selecter1.v"
`include"./control.v"
`include"./ram.v"
`include"./jie.v"

module jiaozhiqi(clk,clk1,en,predate,dateout,datejie,di);
input clk,clk1,en;
output dateout,predate,datejie,di;

wire mshuchu,clk,clk1,w1,r1,dateout,dateout1,dateout2,en,predate,datejie;
wire [2:0] count1;
wire [2:0] add;
wire [2:0] addout1;
wire [2:0] di;


shuru   m0(.q2(mshuchu),.clk(clk1),.en(clk),.preout(predate)); 
counter m1(.clkin(clk),.clkin1(clk1),.countout(count1));
dizhi   m2(.k(add),.q1(di),.clk(clk1),.en(clk));
selecter1 m3(.clksin(clk),.clksin1(clk1),.w(w1),.r(r1));
control m4(.addrin(add),.countin(count1),.datein(mshuchu),.clk(clk),.dateout(dateout1),.addrout(addout1));
ram     m5(.date(dateout1),.dateout(dateout),.addr(addout1),.ena(en),.read(r1),.write(w1));
jie     m6(.datein(dateout),.datejie(datejie),.addr(add),.addrin(count1),.clk1(clk1),.clk(clk));

endmodule