module selecter1(clksin,clksin1,w,r);

input clksin,clksin1;
output w,r;


reg r;

assign w = (!clksin)? clksin1:0;

always@(posedge clksin1 )

if(clksin)

 begin
  r<=1;
 end
  else
  begin
   r<=0;
  
  end
endmodule