module shuru(q2,clk,en,preout);
  
   input clk,en;
   output q2,preout;
   reg q0,q1,q2;
  assign preout=q2;
  always @(posedge clk or posedge en )
    if(en)
     {q2,q1,q0}<=111;
    else
     {q2,q1,q0}<={q2,q1,q0,(q2^q0)};


  endmodule