?? clock.fit.rpt
字號:
; m2_cnt[0] ; 4 ;
; m1_over ; 4 ;
; m1_cnt[2] ; 4 ;
; m1_cnt[3] ; 4 ;
+------------------------------------+---------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; Output enables ; 0 / 6 ( 0 % ) ;
; PIA buffers ; 94 / 288 ( 32 % ) ;
; PIAs ; 94 / 288 ( 32 % ) ;
+----------------------------+-------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 11.75) ; Number of LABs (Total = 6) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 2 ;
; 3 - 5 ; 1 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 1 ;
; 24 - 26 ; 1 ;
; 27 - 29 ; 1 ;
+-----------------------------------------------+-----------------------------+
+----------------------------------------------------------------------+
; LAB Macrocells ;
+----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 8.63) ; Number of LABs (Total = 6) ;
+----------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 3 ;
+----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
+--------------------------+------------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC8 ; rst, m2_cnt[1], m2_cnt[0], m2_cnt[2], m1_over ; m2_cnt[1], m2_cnt[2], m2_over, data4[2] ;
; A ; LC7 ; rst, m2_cnt[2], m2_cnt[1], m2_cnt[0], m1_over ; h1_cnt[0], h1_cnt[1], h1_cnt[3], h1_over, h1_cnt[2] ;
; A ; LC12 ; rst, m2_cnt[2], m2_cnt[0], m2_cnt[1], m1_over ; m2_cnt[1], m2_cnt[2], m2_over, data4[1] ;
; A ; LC15 ; rst, m1_over ; m2_cnt[1], m2_cnt[2], m2_over, data4[0] ;
; A ; LC10 ; rst, s1_cnt[2], s1_cnt[1], s1_cnt[3], s1_cnt[0], lpm_counter:div_cnt_rtl_0|dffs[20] ; s1_cnt[3], s1_cnt[1], s1_over, data4[3] ;
; A ; LC2 ; clk, rst, Select~275, h1_cnt[0], en_xhdl[2], en_xhdl[5], en_xhdl[6], en_xhdl[7], en_xhdl[1], en_xhdl[4], en_xhdl[0], en_xhdl[3], m2_cnt[0], m1_cnt[0], s2_cnt[0], s1_cnt[0] ; Mux~1466, Mux~1470, Mux~1476, Mux~1482, Mux~1487, Mux~1492, Mux~1497 ;
; A ; LC4 ; clk, rst, Select~277, h1_cnt[1], en_xhdl[3], en_xhdl[7], en_xhdl[2], en_xhdl[5], en_xhdl[1], en_xhdl[0], en_xhdl[6], en_xhdl[4], s2_cnt[1], m2_cnt[1], s1_cnt[1], m1_cnt[1] ; Mux~1466, Mux~1470, Mux~1476, Mux~1482, Mux~1487, Mux~1492, Mux~1497 ;
; A ; LC5 ; clk, rst, h1_cnt[2], en_xhdl[2], en_xhdl[5], en_xhdl[6], en_xhdl[7], en_xhdl[1], en_xhdl[4], en_xhdl[0], en_xhdl[3], m2_cnt[2], m1_cnt[2], s2_cnt[2], s1_cnt[2] ; Mux~1466, Mux~1470, Mux~1476, Mux~1482, Mux~1487, Mux~1492, Mux~1497 ;
; A ; LC6 ; rst, s1_cnt[2], s1_cnt[3], s1_cnt[1], s1_cnt[0], lpm_counter:div_cnt_rtl_0|dffs[20] ; s1_cnt[3], s1_cnt[1], s1_cnt[2], s1_over, data4[1] ;
; A ; LC1 ; h2_cnt[0], en_xhdl[2], en_xhdl[5], en_xhdl[6], en_xhdl[7], en_xhdl[1], en_xhdl[4], en_xhdl[0], en_xhdl[3] ; data4[0] ;
; A ; LC9 ; rst, s1_cnt[1], s1_cnt[0], lpm_counter:div_cnt_rtl_0|dffs[20] ; s1_cnt[3], s1_cnt[1], s1_over, data4[2] ;
; A ; LC11 ; rst, s1_cnt[2], s1_cnt[1], s1_cnt[3], s1_cnt[0], lpm_counter:div_cnt_rtl_0|dffs[20] ; s2_cnt[0], s2_cnt[1], s2_cnt[2], S2_over ;
; A ; LC13 ; rst, s2_cnt[2], s2_cnt[0], s2_cnt[1], s1_over ; s2_cnt[1], s2_cnt[2], S2_over, data4[1] ;
; A ; LC14 ; rst, s2_cnt[1], s2_cnt[0], s2_cnt[2], s1_over ; s2_cnt[1], s2_cnt[2], S2_over, data4[2] ;
; A ; LC16 ; rst, s2_cnt[2], s2_cnt[1], s2_cnt[0], s1_over ; m1_cnt[3], m1_cnt[0], m1_cnt[1], m1_cnt[2], m1_over ;
; A ; LC3 ; h2_cnt[1], en_xhdl[3], en_xhdl[7], en_xhdl[2], en_xhdl[5], en_xhdl[1], en_xhdl[0], en_xhdl[6], en_xhdl[4] ; data4[1] ;
; B ; LC21 ; rst, lpm_counter:div_cnt_rtl_0|dffs[20] ; s1_cnt[3], s1_cnt[1], s1_cnt[2], s1_over, data4[0] ;
; B ; LC29 ; rst, s1_over ; s2_cnt[1], s2_cnt[2], S2_over, data4[0] ?? 快捷鍵說明
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