//-----------------------------------------------------------------------------
//   IT51 (Improved-T51)                                                     --
//                                                                           --
//   VERSION: 030723                                                         --
//                                                                           --
//   Contact: yfchen58@gmail.com                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
//  Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)             --
//                          Yung-Fu Chen (yfchen58@ms49.hinet.net)           --
//                                                                           --
//-----------------------------------------------------------------------------
//  FETURE                                                                   --
//     . IT51_top interface is similar to synopsys DW8051                    --
//     . High-Performance 1-Cycle 8051                                       --
//     . instruction compatible with standard DW8051                         --
//     . 256 byte internal data memory                                       --
//     . up to 64KB external data memory                                     --
//     . up to 64KB internal program memory                                  --
//     . export sfr-bus                                                      --
//     . no dual-port memory used                                            --
//     . no watch-dog timer                                                  --
//     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
//     . sleep mode support, refer to DW8051                                 --
//     . no stop mode                                                        --
//     . six external interrupt, refer to DW8051                             --
//     . pass all DW8051 test-pattern                                        --
//     . UART/Timer are not fully tested yet                                 --
//     . no internal tri-state bus                                           --
//     . 2-Cycle MUL Instruction                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51_top (Interface Compatible with Synopsys DW8051)                     --
//     |                                                                     --
//     +-- IT51_core (Control Unit)                                          --
//     |       |                                                             --
//     |       +-- IT51_ALU (ALU)                                            --
//     |               |                                                     --
//     |               +-- IT51_MD (MUL/DIV)                                 --
//     |                                                                     --
//     +-- IT51_Glue (Glue Logic)                                            --
//     |                                                                     --
//     +-- IT51_TC01 (Timer/Counter-1)                                       --
//     |                                                                     --
//     +-- IT51_TC2 (Timer/Counter-2)                                        --
//     |                                                                     --
//     +-- IT51_UART (UART)                                                  --
//                                                                           --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//	http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
module IT51_top (clk, por_n, rst_out_n, stop_mode_n, idle_mode_n, sfr_addr, sfr_data_out, sfr_data_in, sfr_wr, sfr_rd, int0_n, int1_n, int2, int3_n, int4, int5_n, rxd0_in, rxd0_out, txd0, rxd1_in, rxd1_out, txd1, t0, t1, t2, t2ex, t0_out, t1_out, t2_out, mem_addr, mem_data_out, mem_data_in, mem_wr_n, mem_rd_n, iram_addr, iram_data_out, iram_data_in, iram_rd_n, iram_we1_n, iram_we2_n, irom_addr, irom_data_out, irom_rd_n, irom_cs_n);

   // included from package it51_pack
   input clk; 
   input por_n; 
   output rst_out_n; 
   wire rst_out_n;
   output stop_mode_n; 
   wire stop_mode_n;
   output idle_mode_n; 
   wire idle_mode_n;
   output[7:0] sfr_addr; 
   wire[7:0] sfr_addr;
   output[7:0] sfr_data_out; 
   wire[7:0] sfr_data_out;
   input[7:0] sfr_data_in; 
   output sfr_wr; 
   wire sfr_wr;
   output sfr_rd; 
   wire sfr_rd;
   input int0_n; // External Interrupt 0
   input int1_n; // External Interrupt 1
   input int2; // External Interrupt 2
   input int3_n; // External Interrupt 3
   input int4; // External Interrupt 4
   input int5_n; // External Interrupt 5
   input rxd0_in; // serial port0 input
   output rxd0_out; // serial port0 output
   wire rxd0_out;
   output txd0; // serial port0 output
   wire txd0;
   input rxd1_in; // serial port1 input
   output rxd1_out; // serial port1 output
   wire rxd1_out;
   output txd1; // serial port1 output
   wire txd1;
   input t0; // Timer 0 external input
   input t1; // Timer 1 external input
   input t2; // Timer/Counter2 ext.input
   input t2ex; // Timer/Counter2 capt./reload
   output t0_out; // Timer/Counter0 overflow
   wire t0_out;
   output t1_out; // Timer/Counter1 overflow
   wire t1_out;
   output t2_out; // Timer/Counter2 overflow
   wire t2_out;
   output[15:0] mem_addr; 
   wire[15:0] mem_addr;
   output[7:0] mem_data_out; 
   wire[7:0] mem_data_out;
   input[7:0] mem_data_in; 
   output mem_wr_n; 
   wire mem_wr_n;
   output mem_rd_n; 
   wire mem_rd_n;
   output[7:0] iram_addr; 
   wire[7:0] iram_addr;
   input[7:0] iram_data_out; 
   output[7:0] iram_data_in; 
   wire[7:0] iram_data_in;
   output iram_rd_n; 
   wire iram_rd_n;
   output iram_we1_n; 
   wire iram_we1_n;
   output iram_we2_n; 
   wire iram_we2_n;
   output[15:0] irom_addr; 
   wire[15:0] irom_addr;
   input[7:0] irom_data_out; 
   output irom_rd_n; 
   wire irom_rd_n;
   output irom_cs_n; 
   wire irom_cs_n;

   wire Idle_n; 
   wire Stop_n; 
   wire[15:0] ROM_Addr; 
   wire[7:0] ROM_Data; 
   wire[15:0] RAM_Addr; 
   wire[7:0] RAM_RData; 
   wire[7:0] RAM_DO; 
   wire[7:0] RAM_WData; 
   wire RAM_Rd; 
   wire RAM_Wr; 
   wire RAM_WE_n; 
   wire RAM_Sel_n; 
   wire Ex_Sel_i; 
   wire IO_Rd; 
   wire IO_Wr; 
   wire[6:0] IO_Addr; 
   wire[6:0] IO_Addr_r; 
   wire[7:0] IO_WData; 
   wire[7:0] IO_RData; 
   wire P0_Sel; 
   wire P1_Sel; 
   wire P2_Sel; 
   wire P3_Sel; 
   wire TMOD_Sel; 
   wire TL0_Sel; 
   wire TL1_Sel; 
   wire TH0_Sel; 
   wire TH1_Sel; 
   wire T2CON_Sel; 
   wire RCAP2L_Sel; 
   wire RCAP2H_Sel; 
   wire TL2_Sel; 
   wire TH2_Sel; 
   wire SCON_Sel; 
   wire SBUF_Sel; 
   wire P0_Wr; 
   wire P1_Wr; 
   wire P2_Wr; 
   wire P3_Wr; 
   wire TMOD_Wr; 
   wire TL0_Wr; 
   wire TL1_Wr; 
   wire TH0_Wr; 
   wire TH1_Wr; 
   wire T2CON_Wr; 
   wire RCAP2L_Wr; 
   wire RCAP2H_Wr; 
   wire TL2_Wr; 
   wire TH2_Wr; 
   wire SCON_Wr; 
   wire SBUF_Wr; 
   wire UseR2; 
   wire UseT2; 
   wire UART_Clk; 
   wire R0; 
   wire R1; 
   wire SMOD; 
   wire[10:0] Int_Trig; 
   wire[10:0] Int_Acc; 
   wire RI; 
   wire TI; 
   wire OF0; 
   wire OF1;