?? it51_glue.v
字號:
Int3_r <= 2'b11 ;
Int4_r <= 2'b00 ;
Int5_r <= 2'b11 ;
end
else
begin
Int0_r <= {Int0_r[0], INT0} ;
Int1_r <= {Int1_r[0], INT1} ;
Int2_r <= {Int2_r[0], INT2} ;
Int3_r <= {Int3_r[0], INT3} ;
Int4_r <= {Int4_r[0], INT4} ;
Int5_r <= {Int5_r[0], INT5} ;
if (IO_Wr == 1'b1 & IO_Addr_r == 7'b1101000)
begin
EIE <= IO_WData ;
end
if (IO_Wr == 1'b1 & IO_Addr_r == 7'b0010001)
begin
EXIF <= IO_WData ;
end
else
begin
if ((Int_Acc[10]) == 1'b1)
begin
EXIF[7] <= 1'b0 ;
end
else if (Int5_r == 2'b10)
begin
EXIF[7] <= 1'b1 ;
end
if ((Int_Acc[9]) == 1'b1)
begin
EXIF[6] <= 1'b0 ;
end
else if (Int4_r == 2'b01)
begin
EXIF[6] <= 1'b1 ;
end
if ((Int_Acc[8]) == 1'b1)
begin
EXIF[5] <= 1'b0 ;
end
else if (Int3_r == 2'b10)
begin
EXIF[5] <= 1'b1 ;
end
if ((Int_Acc[7]) == 1'b1)
begin
EXIF[4] <= 1'b0 ;
end
else if (Int2_r == 2'b01)
begin
EXIF[4] <= 1'b1 ;
end
end
if (IO_Wr == 1'b1 & IO_Addr_r == 7'b0101000)
begin
IE <= IO_WData ;
end
if (IO_Wr == 1'b1 & IO_Addr_r == 7'b0001000)
begin
TCON <= IO_WData ;
end
if (OF0 == 1'b1)
begin
TCON[5] <= 1'b1 ;
end
if ((Int_Acc[1]) == 1'b1)
begin
TCON[5] <= 1'b0 ;
end
if (OF1 == 1'b1)
begin
TCON[7] <= 1'b1 ;
end
if ((Int_Acc[3]) == 1'b1)
begin
TCON[7] <= 1'b0 ;
end
if ((TCON[0]) == 1'b1)
begin
// External interrupts
if ((Int_Acc[0]) == 1'b1)
begin
TCON[1] <= 1'b0 ;
end
if (Int0_r == 2'b10)
begin
TCON[1] <= 1'b1 ;
end
end
else
begin
TCON[1] <= ~Int0_r[0] ;
end
if ((TCON[2]) == 1'b1)
begin
if ((Int_Acc[2]) == 1'b1)
begin
TCON[3] <= 1'b0 ;
end
if (Int1_r == 2'b10)
begin
TCON[3] <= 1'b1 ;
end
end
else
begin
TCON[3] <= ~Int1_r[0] ;
end
end
end
assign Int_Trig_i[0] = ((IE[7]) == 1'b0 | (IE[0]) == 1'b0) ? 1'b0 : ((TCON[0]) == 1'b0) ? ~Int0_r[1] : TCON[1] ;
assign Int_Trig_i[1] = ((IE[7]) == 1'b1 & (IE[1]) == 1'b1 & (TCON[5]) == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[2] = ((IE[7]) == 1'b0 | (IE[2]) == 1'b0) ? 1'b0 : ((TCON[2]) == 1'b0) ? ~Int1_r[1] : TCON[3] ;
assign Int_Trig_i[3] = ((IE[7]) == 1'b1 & (IE[3]) == 1'b1 & (TCON[7]) == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[4] = ((IE[7]) == 1'b1 & (IE[4]) == 1'b1 & (RI == 1'b1 | TI == 1'b1)) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[5] = ((IE[7]) == 1'b1 & (IE[5]) == 1'b1 & OF2 == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[6] = 1'b0 ;
assign Int_Trig_i[7] = ((EIE[0]) == 1'b1 & (EXIF[4]) == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[8] = ((EIE[1]) == 1'b1 & (EXIF[5]) == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[9] = ((EIE[2]) == 1'b1 & (EXIF[6]) == 1'b1) ? 1'b1 : 1'b0 ;
assign Int_Trig_i[10] = ((EIE[3]) == 1'b1 & (EXIF[7]) == 1'b1) ? 1'b1 : 1'b0 ;
//-----------------------
// TMOD
assign TMOD_Sel = TMOD_Sel_i ;
assign TMOD_Sel_i = (IO_Addr == 7'b0001001) ? 1'b1 : 1'b0 ;
assign TMOD_Wr = (TMOD_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TMOD_Sel_r <= 1'b0 ;
end
else
begin
TMOD_Sel_r <= TMOD_Sel_i ;
end
end
//-----------------------
// TL0
assign TL0_Sel = TL0_Sel_i ;
assign TL0_Sel_i = (IO_Addr == 7'b0001010) ? 1'b1 : 1'b0 ;
assign TL0_Wr = (TL0_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TL0_Sel_r <= 1'b0 ;
end
else
begin
TL0_Sel_r <= TL0_Sel_i ;
end
end
//-----------------------
// TL1
assign TL1_Sel = TL0_Sel_i ;
assign TL1_Sel_i = (IO_Addr == 7'b0001011) ? 1'b1 : 1'b0 ;
assign TL1_Wr = (TL1_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TL1_Sel_r <= 1'b0 ;
end
else
begin
TL1_Sel_r <= TL1_Sel_i ;
end
end
//-----------------------
// TH0
assign TH0_Sel = TH0_Sel_i ;
assign TH0_Sel_i = (IO_Addr == 7'b0001100) ? 1'b1 : 1'b0 ;
assign TH0_Wr = (TH0_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TH0_Sel_r <= 1'b0 ;
end
else
begin
TH0_Sel_r <= TH0_Sel_i ;
end
end
//-----------------------
// TH1
assign TH1_Sel = TH1_Sel_i ;
assign TH1_Sel_i = (IO_Addr == 7'b0001101) ? 1'b1 : 1'b0 ;
assign TH1_Wr = (TH1_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TH1_Sel_r <= 1'b0 ;
end
else
begin
TH1_Sel_r <= TH1_Sel_i ;
end
end
//-----------------------
// T2CON
assign T2CON_Sel = T2CON_Sel_i ;
assign T2CON_Sel_i = (IO_Addr == 7'b1001000) ? 1'b1 : 1'b0 ;
assign T2CON_Wr = (T2CON_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
T2CON_Sel_r <= 1'b0 ;
end
else
begin
T2CON_Sel_r <= T2CON_Sel_i ;
end
end
//-----------------------
// RCAP2L
assign RCAP2L_Sel = RCAP2L_Sel_i ;
assign RCAP2L_Sel_i = (IO_Addr == 7'b1001010) ? 1'b1 : 1'b0 ;
assign RCAP2L_Wr = (RCAP2L_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
RCAP2L_Sel_r <= 1'b0 ;
end
else
begin
RCAP2L_Sel_r <= RCAP2L_Sel_i ;
end
end
//-----------------------
// RCAP2H
assign RCAP2H_Sel = RCAP2H_Sel_i ;
assign RCAP2H_Sel_i = (IO_Addr == 7'b1001011) ? 1'b1 : 1'b0 ;
assign RCAP2H_Wr = (RCAP2H_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
RCAP2H_Sel_r <= 1'b0 ;
end
else
begin
RCAP2H_Sel_r <= RCAP2H_Sel_i ;
end
end
//-----------------------
// TL2
assign TL2_Sel = TL2_Sel_i ;
assign TL2_Sel_i = (IO_Addr == 7'b1001100) ? 1'b1 : 1'b0 ;
assign TL2_Wr = (TL2_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TL2_Sel_r <= 1'b0 ;
end
else
begin
TL2_Sel_r <= TL2_Sel_i ;
end
end
//-----------------------
// TH2
assign TH2_Sel = TH2_Sel_i ;
assign TH2_Sel_i = (IO_Addr == 7'b1001101) ? 1'b1 : 1'b0 ;
assign TH2_Wr = (TH2_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
TH2_Sel_r <= 1'b0 ;
end
else
begin
TH2_Sel_r <= TH2_Sel_i ;
end
end
//-----------------------
// SCON
assign SCON_Sel = SCON_Sel_i ;
assign SCON_Sel_i = (IO_Addr == 7'b0011000) ? 1'b1 : 1'b0 ;
assign SCON_Wr = (SCON_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
SCON_Sel_r <= 1'b0 ;
end
else
begin
SCON_Sel_r <= SCON_Sel_i ;
end
end
//-----------------------
// SBUF
assign SBUF_Sel = SBUF_Sel_i ;
assign SBUF_Sel_i = (IO_Addr == 7'b0011001) ? 1'b1 : 1'b0 ;
assign SBUF_Wr = (SBUF_Sel_r == 1'b1 & IO_Wr == 1'b1) ? 1'b1 : 1'b0 ;
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
SBUF_Sel_r <= 1'b0 ;
end
else
begin
SBUF_Sel_r <= SBUF_Sel_i ;
end
end
endmodule
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