//-----------------------------------------------------------------------------
//   IT51 (Improved-T51)                                                     --
//                                                                           --
//   VERSION: 030723                                                         --
//                                                                           --
//   Contact: yfchen58@gmail.com                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
//  Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)             --
//                          Yung-Fu Chen (yfchen58@ms49.hinet.net)           --
//                                                                           --
//-----------------------------------------------------------------------------
//  FETURE                                                                   --
//     . IT51_top interface is similar to synopsys DW8051                    --
//     . High-Performance 1-Cycle 8051                                       --
//     . instruction compatible with standard DW8051                         --
//     . 256 byte internal data memory                                       --
//     . up to 64KB external data memory                                     --
//     . up to 64KB internal program memory                                  --
//     . export sfr-bus                                                      --
//     . no dual-port memory used                                            --
//     . no watch-dog timer                                                  --
//     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
//     . sleep mode support, refer to DW8051                                 --
//     . no stop mode                                                        --
//     . six external interrupt, refer to DW8051                             --
//     . pass all DW8051 test-pattern                                        --
//     . UART/Timer are not fully tested yet                                 --
//     . no internal tri-state bus                                           --
//     . 2-Cycle MUL Instruction                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51_top (Interface Compatible with Synopsys DW8051)                     --
//     |                                                                     --
//     +-- IT51_core (Control Unit)                                          --
//     |       |                                                             --
//     |       +-- IT51_ALU (ALU)                                            --
//     |               |                                                     --
//     |               +-- IT51_MD (MUL/DIV)                                 --
//     |                                                                     --
//     +-- IT51_Glue (Glue Logic)                                            --
//     |                                                                     --
//     +-- IT51_TC01 (Timer/Counter-1)                                       --
//     |                                                                     --
//     +-- IT51_TC2 (Timer/Counter-2)                                        --
//     |                                                                     --
//     +-- IT51_UART (UART)                                                  --
//                                                                           --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//	http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
// use IEEE.numeric_std.all;
module IT51_UART (Clk, Rst_n, UseR2, UseT2, BaudC2, BaudC1, SC_Sel, SB_Sel, SC_Wr, SB_Wr, SMOD, Data_In, Data_Out, RXD, RXD_IsO, RXD_O, TXD, RI, TI);

   input Clk; 
   input Rst_n; 
   input UseR2; 
   input UseT2; 
   input BaudC2; 
   input BaudC1; 
   input SC_Sel; 
   input SB_Sel; 
   input SC_Wr; 
   input SB_Wr; 
   input SMOD; 
   input[7:0] Data_In; 
   output[7:0] Data_Out; 
   wire[7:0] Data_Out;
   input RXD; 
   output RXD_IsO; 
   wire RXD_IsO;
   output RXD_O; 
   reg RXD_O;
   output TXD; 
   wire TXD;
   output RI; 
   wire RI;
   output TI; 
   wire TI;

   reg[7:0] SCON; 
   reg[7:0] SBUF; 
   wire Baud16R_i; 
   wire Baud16T_i; 
   reg BaudC1_g; 
   reg BaudFix; 
   reg[3:0] Bit_Phase; 
   reg RX_Filtered; 
   reg[8:0] RX_ShiftReg; 
   reg[3:0] RX_Bit_Cnt; 
   reg RX_Shifting; 
   //	signal	Overflow_t		: std_logic;
   reg TXD_i; 
   reg TX_Tick; 
   reg TX_Start; 
   reg TX_Shifting; 
   reg[7:0] TX_Data; 
   reg[8:0] TX_ShiftReg; 
   reg[3:0] TX_Bit_Cnt; 
   reg Tick6; 

   // Registers
   assign Data_Out = (SC_Sel == 1'b1) ? SCON : (SB_Sel == 1'b1) ? SBUF : 8'bxxxxxxxx ;

   always @(negedge Rst_n or posedge Clk)
   begin
      if (Rst_n == 1'b0)
      begin
         SCON[7:3] <= 5'b00000 ; 
      end
      else
      begin
         if (SC_Wr == 1'b1)
         begin
            SCON[7:3] <= Data_In[7:3] ; 
         end 
      end 
   end 
   assign Baud16T_i = ((SCON[6]) == 1'b1) ? (UseT2 & BaudC2) | (~UseT2 & BaudC1 & BaudC1_g) : BaudFix ;
   assign Baud16R_i = ((SCON[6]) == 1'b1) ? (UseR2 & BaudC2) | (~UseR2 & BaudC1 & BaudC1_g) : BaudFix ;

   // Baud x 16 clock generator
   always @(posedge Clk or negedge Rst_n)
   begin
      reg[5:0] Baud_Cnt; 
      if (Rst_n == 1'b0)
      begin
         Baud_Cnt <= 6'b000000; 
         BaudFix <= 1'b0 ; 
         BaudC1_g <= 1'b0 ; 
      end
      else
      begin
         BaudFix <= 1'b0 ; 
         BaudC1_g <= 1'b1 ; 
         if (SMOD == 1'b0 & BaudC1 == 1'b1)
         begin
            BaudC1_g <= ~BaudC1_g ; 
         end 
         if (Baud_Cnt[4:0] == 5'b11111 & (SMOD == 1'b1 | (Baud_Cnt[5]) == 1'b1))
         begin
            BaudFix <= 1'b1 ; 
         end 
         Baud_Cnt <= Baud_Cnt - 1; 
      end 
   end 

   // Input filter
   always @(posedge Clk or negedge Rst_n)
   begin
      reg[1:0] Samples; 
      if (Rst_n == 1'b0)
      begin
         Samples <= 2'b11; 
         RX_Filtered <= 1'b1 ; 
      end
      else
      begin
         if (Baud16R_i == 1'b1)
         begin
            Samples[1] <= Samples[0]; 
            Samples[0] <= RXD; 
         end 
         if (Samples == 2'b00)
         begin
            RX_Filtered <= 1'b0 ; 
         end 
         if (Samples == 2'b11)
         begin
            RX_Filtered <= 1'b1 ; 
         end 
      end 
   end 
   // Receive state machine
   assign RI = SCON[0] ;

   always @(posedge Clk or negedge Rst_n)
   begin
      if (Rst_n == 1'b0)
      begin
         SCON[0] <= 1'b0 ; 
         SCON[2] <= 1'b0 ; 
         SBUF <= 8'b00000000 ; 
         Bit_Phase <= 4'b0000 ; 
         RX_ShiftReg[8:0] <= 9'b000000000 ; 
         RX_Bit_Cnt <= 0 ; 
         RX_Shifting <= 1'b0 ; 
      end
      else
      begin
         if (SC_Wr == 1'b1)