//-----------------------------------------------------------------------------
//   IT51 (Improved-T51)                                                     --
//                                                                           --
//   VERSION: 030723                                                         --
//                                                                           --
//   Contact: yfchen58@gmail.com                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller)       --
//  Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)             --
//                          Yung-Fu Chen (yfchen58@ms49.hinet.net)           --
//                                                                           --
//-----------------------------------------------------------------------------
//  FETURE                                                                   --
//     . IT51_top interface is similar to synopsys DW8051                    --
//     . High-Performance 1-Cycle 8051                                       --
//     . instruction compatible with standard DW8051                         --
//     . 256 byte internal data memory                                       --
//     . up to 64KB external data memory                                     --
//     . up to 64KB internal program memory                                  --
//     . export sfr-bus                                                      --
//     . no dual-port memory used                                            --
//     . no watch-dog timer                                                  --
//     . dual DPTR (DPTR0, DPTR1), refer to DW8051                           --
//     . sleep mode support, refer to DW8051                                 --
//     . no stop mode                                                        --
//     . six external interrupt, refer to DW8051                             --
//     . pass all DW8051 test-pattern                                        --
//     . UART/Timer are not fully tested yet                                 --
//     . no internal tri-state bus                                           --
//     . 2-Cycle MUL Instruction                                             --
//                                                                           --
//-----------------------------------------------------------------------------
//                                                                           --
//  IT51_top (Interface Compatible with Synopsys DW8051)                     --
//     |                                                                     --
//     +-- IT51_core (Control Unit)                                          --
//     |       |                                                             --
//     |       +-- IT51_ALU (ALU)                                            --
//     |               |                                                     --
//     |               +-- IT51_MD (MUL/DIV)                                 --
//     |                                                                     --
//     +-- IT51_Glue (Glue Logic)                                            --
//     |                                                                     --
//     +-- IT51_TC01 (Timer/Counter-1)                                       --
//     |                                                                     --
//     +-- IT51_TC2 (Timer/Counter-2)                                        --
//     |                                                                     --
//     +-- IT51_UART (UART)                                                  --
//                                                                           --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
//	http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
//
module IT51_MD (Clk, Rst_n, ACC, B, Mul_Q, Mul_OV, Div_Q, Div_OV, Div_Rdy);

   // included from package it51_pack
   input Clk; 
   input Rst_n; 
   input[7:0] ACC; 
   input[7:0] B; 
   output[15:0] Mul_Q; 
   reg[15:0] Mul_Q;
   output Mul_OV; 
   reg Mul_OV;
   output[15:0] Div_Q; 
   reg[15:0] Div_Q;
   output Div_OV; 
   reg Div_OV;
   output Div_Rdy; 
   reg Div_Rdy;

   reg[7:0] Old_ACC; 
   reg[7:0] Old_B; 
   // YFC
   reg[3:0] Cnt; 

   always @(posedge Clk or negedge Rst_n)
   begin
      if (Rst_n == 1'b0)
      begin
         Cnt <= {4{1'b0}} ; 
      end
      else
      begin
         if (Old_ACC != ACC | Old_B != B)
         begin
            Cnt <= 4'b0000 ; 
         end
         else
         begin
            Cnt <= Cnt + 1 ; 
         end 
      end 
   end 

   always @(ACC or B)
   begin
      reg[15:0] Tmp; 
      //Tmp = unsigned(ACC) * unsigned(B); 
      Tmp = ACC * B; 
      Mul_Q = Tmp ; 
      if (Tmp[15:8] == 8'b00000000)
      begin
         Mul_OV = 1'b0 ; 
      end
      else
      begin
         Mul_OV = 1'b1 ; 
      end 
   end 

   always @(posedge Clk or negedge Rst_n)
   begin
      reg[15:0] Tmp1; 
      reg[8:0] Tmp2; 
      reg[8:0] Tmp3; 
      if (Rst_n == 1'b0)
      begin
         Old_ACC <= {8{1'b0}} ; 
         Old_B <= {8{1'b0}} ; 
         Div_Rdy <= 1'b0 ; 
         Div_OV <= 1'b0 ; 
         Div_Q <= {16{1'b0}} ; 
         Tmp1 <= {16{1'b0}}; 
         Tmp2 <= {9{1'b0}}; 
         Tmp3 <= {9{1'b0}}; 
      end
      else
      begin
         Old_ACC <= ACC ; 
         Old_B <= B ; 
         Div_Rdy <= 1'b0 ; 
         Div_OV <= 1'b0 ; 
         // YFC
         //		variable Cnt	: unsigned(3 downto 0);
         if ((Cnt[3]) == 1'b1)
         begin
            Div_Rdy <= 1'b1 ; 
         end 
         if (B == 8'b00000000)
         begin
            // YFC >>>
            // BUG (op_84)
            Div_Q[7:0] <= {8{1'b1}} ; 
            //Div_Q[15:8] <= std_logic_vector(ACC) ; 
            Div_Q[15:8] <= ACC ; 
            Div_OV <= 1'b1 ; 
            Div_Rdy <= 1'b1 ; 
         end
         //- <<<
         else if (ACC == B)
         begin
            Div_Q[7:0] <= 8'b00000001 ; 
            Div_Q[15:8] <= 8'b00000000 ; 
         end
         else if (ACC < B)
         begin
            Div_Q[7:0] <= 8'b00000000 ; 
            //Div_Q[15:8] <= std_logic_vector(ACC) ; 
            Div_Q[15:8] <= ACC ; 
            Div_Rdy <= 1'b1 ; 
         end
         else if ((Cnt[3]) == 1'b0)
         begin
            Tmp1[15:1] <= Tmp1[14:0]; 
            Tmp1[0] <= 1'b0; 
            Tmp2 <= ({1'b1, Tmp1[15:8]}) - Tmp3; 
            if ((Tmp2[8]) == 1'b1)
            begin
               Tmp1[0] <= 1'b1; 
               Tmp1[15:8] <= Tmp2[7:0]; 
            end 
            //Div_Q <= std_logic_Vector(Tmp1) ; 
            Div_Q <= Tmp1; 
         end 
         if (Old_ACC != ACC | Old_B != B)
         begin
            //Tmp1[7:0] = unsigned(ACC); 
            Tmp1[7:0] <= ACC; 
            Tmp1[15:8] <= 8'b00000000; 
            //				Tmp3 := "0" & unsigned(B);
            //Tmp3 = unsigned({1'b0, B}); 
            Tmp3 <= {1'b0, B}; 
            // YFC
            //				Cnt := "0000";
            Div_Rdy <= 1'b0 ; 
         end
         //			else
         //				cnt := cnt + 1; 
      end 
   end 
endmodule