?? it51_tc2.v
字號(hào):
//-----------------------------------------------------------------------------
// IT51 (Improved-T51) --
// --
// VERSION: 030723 --
// --
// Contact: yfchen58@gmail.com --
// --
//-----------------------------------------------------------------------------
// --
// IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller) --
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --
// Yung-Fu Chen (yfchen58@ms49.hinet.net) --
// --
//-----------------------------------------------------------------------------
// FETURE --
// . IT51_top interface is similar to synopsys DW8051 --
// . High-Performance 1-Cycle 8051 --
// . instruction compatible with standard DW8051 --
// . 256 byte internal data memory --
// . up to 64KB external data memory --
// . up to 64KB internal program memory --
// . export sfr-bus --
// . no dual-port memory used --
// . no watch-dog timer --
// . dual DPTR (DPTR0, DPTR1), refer to DW8051 --
// . sleep mode support, refer to DW8051 --
// . no stop mode --
// . six external interrupt, refer to DW8051 --
// . pass all DW8051 test-pattern --
// . UART/Timer are not fully tested yet --
// . no internal tri-state bus --
// . 2-Cycle MUL Instruction --
// --
//-----------------------------------------------------------------------------
// --
// IT51_top (Interface Compatible with Synopsys DW8051) --
// | --
// +-- IT51_core (Control Unit) --
// | | --
// | +-- IT51_ALU (ALU) --
// | | --
// | +-- IT51_MD (MUL/DIV) --
// | --
// +-- IT51_Glue (Glue Logic) --
// | --
// +-- IT51_TC01 (Timer/Counter-1) --
// | --
// +-- IT51_TC2 (Timer/Counter-2) --
// | --
// +-- IT51_UART (UART) --
// --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
module IT51_TC2 (Clk, Rst_n, T2, T2EX, C_Sel, CH_Sel, CL_Sel, H_Sel, L_Sel, C_Wr, CH_Wr, CL_Wr, H_Wr, L_Wr, Data_In, Data_Out, UseR2, UseT2, UART_Clk, F);
input Clk;
input Rst_n;
input T2;
input T2EX;
input C_Sel;
input CH_Sel;
input CL_Sel;
input H_Sel;
input L_Sel;
input C_Wr;
input CH_Wr;
input CL_Wr;
input H_Wr;
input L_Wr;
input[7:0] Data_In;
output[7:0] Data_Out;
wire[7:0] Data_Out;
output UseR2;
wire UseR2;
output UseT2;
wire UseT2;
output UART_Clk;
reg UART_Clk;
output F;
wire F;
reg[7:0] TCON;
reg[15:0] Cnt;
reg[15:0] Cpt;
reg Tick;
reg Tick12;
reg Capture;
assign F = TCON[6] ;
assign UseR2 = TCON[5] ;
assign UseT2 = TCON[4] ;
// Registers and counter
assign Data_Out = (H_Sel == 1'b1) ? Cnt[15:8] : (L_Sel == 1'b1) ? Cnt[7:0] : (CH_Sel == 1'b1) ? Cpt[15:8] : (CL_Sel == 1'b1) ? Cpt[7:0] : (C_Sel == 1'b1) ? TCON : 8'bxxxxxxxx ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
TCON <= {8{1'b0}} ;
Cnt <= {16{1'b0}} ;
Cpt <= {16{1'b0}} ;
UART_Clk <= 1'b0 ;
end
else
begin
TCON[7] <= 1'b0 ;
UART_Clk <= 1'b0 ;
if (Tick == 1'b1)
begin
Cnt <= Cnt + 1 ;
if (Cnt == 16'b1111111111111111)
begin
if ((TCON[4]) == 1'b0 & (TCON[5]) == 1'b0)
begin
TCON[7] <= 1'b1 ;
end
if ((TCON[0]) == 1'b0 | (TCON[4]) == 1'b1 | (TCON[5]) == 1'b1)
begin
Cnt <= Cpt ;
end
UART_Clk <= 1'b1 ;
end
end
if (Capture == 1'b1 & (TCON[0]) == 1'b0 & (TCON[4]) == 1'b0 & (TCON[5]) == 1'b0)
begin
Cnt <= Cpt ;
TCON[6] <= 1'b1 ;
end
if (Capture == 1'b1 & (TCON[0]) == 1'b1 & (TCON[4]) == 1'b0 & (TCON[5]) == 1'b0)
begin
Cpt <= Cnt ;
TCON[6] <= 1'b1 ;
end
// Register write
if (C_Wr == 1'b1)
begin
TCON <= Data_In ;
end
if (H_Wr == 1'b1)
begin
Cnt[15:8] <= Data_In ;
end
if (L_Wr == 1'b1)
begin
Cnt[7:0] <= Data_In ;
end
if (CH_Wr == 1'b1)
begin
Cpt[15:8] <= Data_In ;
end
if (CL_Wr == 1'b1)
begin
Cpt[7:0] <= Data_In ;
end
end
end
// Tick generator
always @(posedge Clk or negedge Rst_n)
begin
reg[3:0] Prescaler;
reg[1:0] T_r;
reg[1:0] E_r;
if (Rst_n == 1'b0)
begin
Prescaler <= {4{1'b0}};
Tick <= 1'b0 ;
Tick12 <= 1'b0 ;
Capture <= 1'b0 ;
T_r <= 2'b00;
// YFC
E_r <= 2'b00;
end
else
begin
Tick <= 1'b0 ;
Tick12 <= 1'b0 ;
Capture <= 1'b0 ;
if ((TCON[2]) == 1'b1)
begin
if ((TCON[1]) == 1'b1)
begin
Tick <= T_r[0] & ~T_r[1] ;
end
else
begin
Tick <= Tick12 ;
end
end
if ((TCON[3]) == 1'b1)
begin
Capture <= E_r[1] & ~E_r[0] ;
end
T_r[1] <= T_r[0];
T_r[0] <= T2;
E_r[1] <= E_r[0];
E_r[0] <= T2EX;
if (((Prescaler[0]) == 1'b1 & ((TCON[4]) == 1'b1 | (TCON[5]) == 1'b1)) | Prescaler == 4'b1011)
begin
Prescaler <= 4'b0000;
Tick12 <= 1'b1 ;
end
else
begin
Prescaler <= Prescaler + 1;
end
end
// if FastCount then
// Tick12 <= '1';
// end if;
end
endmodule
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