?? it51_tc01.v
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//-----------------------------------------------------------------------------
// IT51 (Improved-T51) --
// --
// VERSION: 030723 --
// --
// Contact: yfchen58@gmail.com --
// --
//-----------------------------------------------------------------------------
// --
// IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller) --
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --
// Yung-Fu Chen (yfchen58@ms49.hinet.net) --
// --
//-----------------------------------------------------------------------------
// FETURE --
// . IT51_top interface is similar to synopsys DW8051 --
// . High-Performance 1-Cycle 8051 --
// . instruction compatible with standard DW8051 --
// . 256 byte internal data memory --
// . up to 64KB external data memory --
// . up to 64KB internal program memory --
// . export sfr-bus --
// . no dual-port memory used --
// . no watch-dog timer --
// . dual DPTR (DPTR0, DPTR1), refer to DW8051 --
// . sleep mode support, refer to DW8051 --
// . no stop mode --
// . six external interrupt, refer to DW8051 --
// . pass all DW8051 test-pattern --
// . UART/Timer are not fully tested yet --
// . no internal tri-state bus --
// . 2-Cycle MUL Instruction --
// --
//-----------------------------------------------------------------------------
// --
// IT51_top (Interface Compatible with Synopsys DW8051) --
// | --
// +-- IT51_core (Control Unit) --
// | | --
// | +-- IT51_ALU (ALU) --
// | | --
// | +-- IT51_MD (MUL/DIV) --
// | --
// +-- IT51_Glue (Glue Logic) --
// | --
// +-- IT51_TC01 (Timer/Counter-1) --
// | --
// +-- IT51_TC2 (Timer/Counter-2) --
// | --
// +-- IT51_UART (UART) --
// --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
// use IEEE.numeric_std.all;
module IT51_TC01 (Clk, Rst_n, T0, T1, INT0, INT1, M_Sel, H0_Sel, L0_Sel, H1_Sel, L1_Sel, R0, R1, M_Wr, H0_Wr, L0_Wr, H1_Wr, L1_Wr, Data_In, Data_Out, OF0, OF1);
input Clk;
input Rst_n;
input T0;
input T1;
input INT0;
input INT1;
input M_Sel;
input H0_Sel;
input L0_Sel;
input H1_Sel;
input L1_Sel;
input R0;
input R1;
input M_Wr;
input H0_Wr;
input L0_Wr;
input H1_Wr;
input L1_Wr;
input[7:0] Data_In;
output[7:0] Data_Out;
wire[7:0] Data_Out;
output OF0;
reg OF0;
output OF1;
reg OF1;
reg[7:0] TMOD;
reg[15:0] Cnt0;
reg[15:0] Cnt1;
reg Tick0;
reg Tick1;
reg Tick12;
// Registers and counter
assign Data_Out = (H0_Sel == 1'b1) ? Cnt0[15:8] : (L0_Sel == 1'b1) ? Cnt0[7:0] : (H1_Sel == 1'b1) ? Cnt1[15:8] : (L1_Sel == 1'b1) ? Cnt1[7:0] : (M_Sel == 1'b1) ? TMOD : 8'bxxxxxxxx ;
always @(negedge Rst_n or posedge Clk)
begin
if (Rst_n == 1'b0)
begin
TMOD <= {8{1'b0}} ;
Cnt0 <= {16{1'b0}} ;
Cnt1 <= {16{1'b0}} ;
OF0 <= 1'b0 ;
OF1 <= 1'b0 ;
end
else
begin
OF0 <= 1'b0 ;
OF1 <= 1'b0 ;
if (TMOD[1:0] == 2'b00)
begin
if (Tick0 == 1'b1)
begin
Cnt0[12:0] <= Cnt0[12:0] + 1 ;
if (Cnt0[12:0] == 13'b1111111111111)
begin
OF0 <= 1'b1 ;
end
end
end
if (TMOD[5:4] == 2'b00)
begin
if (Tick1 == 1'b1)
begin
Cnt1[12:0] <= Cnt1[12:0] + 1 ;
if (Cnt1[12:0] == 13'b1111111111111)
begin
OF1 <= 1'b1 ;
end
end
end
if (TMOD[1:0] == 2'b01)
begin
if (Tick0 == 1'b1)
begin
Cnt0 <= Cnt0 + 1 ;
if (Cnt0 == 16'b1111111111111111)
begin
OF0 <= 1'b1 ;
end
end
end
if (TMOD[5:4] == 2'b01)
begin
if (Tick1 == 1'b1)
begin
Cnt1 <= Cnt1 + 1 ;
if (Cnt1 == 16'b1111111111111111)
begin
OF1 <= 1'b1 ;
end
end
end
if (TMOD[1:0] == 2'b10)
begin
if (Tick0 == 1'b1)
begin
Cnt0[7:0] <= Cnt0[7:0] + 1 ;
if (Cnt0[7:0] == 8'b11111111)
begin
Cnt0[7:0] <= Cnt0[15:8] ;
OF0 <= 1'b1 ;
end
end
end
if (TMOD[5:4] == 2'b10)
begin
if (Tick1 == 1'b1)
begin
Cnt1[7:0] <= Cnt1[7:0] + 1 ;
if (Cnt1[7:0] == 8'b11111111)
begin
Cnt1[7:0] <= Cnt1[15:8] ;
OF1 <= 1'b1 ;
end
end
end
if (TMOD[1:0] == 2'b11)
begin
if (Tick0 == 1'b1)
begin
Cnt0[7:0] <= Cnt0[7:0] + 1 ;
if (Cnt0[7:0] == 8'b11111111)
begin
OF0 <= 1'b1 ;
end
end
OF1 <= 1'b0 ;
if (R1 == 1'b1 & Tick12 == 1'b1)
begin
Cnt0[15:8] <= Cnt0[15:8] + 1 ;
if (Cnt1[15:8] == 8'b11111111)
begin
OF1 <= 1'b1 ;
end
end
end
// Register write
if (M_Wr == 1'b1)
begin
TMOD <= Data_In ;
end
if (H0_Wr == 1'b1)
begin
Cnt0[15:8] <= Data_In ;
end
if (L0_Wr == 1'b1)
begin
Cnt0[7:0] <= Data_In ;
end
if (H1_Wr == 1'b1)
begin
Cnt1[15:8] <= Data_In ;
end
if (L1_Wr == 1'b1)
begin
Cnt1[7:0] <= Data_In ;
end
end
end
// Tick generator
always @(posedge Clk or negedge Rst_n)
begin
reg[3:0] Prescaler;
reg[1:0] T0_r;
reg[1:0] T1_r;
reg[1:0] I0_r;
reg[1:0] I1_r;
if (Rst_n == 1'b0)
begin
Prescaler <= {4{1'b0}};
Tick0 <= 1'b0 ;
Tick1 <= 1'b0 ;
Tick12 <= 1'b0 ;
T0_r <= 2'b00;
T1_r <= 2'b00;
I0_r <= 2'b00;
I1_r <= 2'b00;
end
else
begin
Tick0 <= 1'b0 ;
Tick1 <= 1'b0 ;
Tick12 <= 1'b0 ;
if (R0 == 1'b1 & ((I0_r[1]) == 1'b1 | (TMOD[3]) == 1'b0))
begin
if ((TMOD[2]) == 1'b1)
begin
Tick0 <= T0_r[0] & ~T0_r[1] ;
end
else
begin
Tick0 <= Tick12 ;
end
end
if (R1 == 1'b1 & ((I1_r[1]) == 1'b1 | (TMOD[7]) == 1'b0))
begin
if ((TMOD[6]) == 1'b1)
begin
Tick1 <= T1_r[0] & ~T1_r[1] ;
end
else
begin
Tick1 <= Tick12 ;
end
end
T0_r[1] <= T0_r[0];
T1_r[1] <= T1_r[0];
T0_r[0] <= T0;
T1_r[0] <= T1;
I0_r[1] <= I0_r[0];
I1_r[1] <= I1_r[0];
I0_r[0] <= INT0;
I1_r[0] <= INT1;
if (Prescaler == 4'b1011)
begin
Prescaler <= 4'b0000;
Tick12 <= 1'b1 ;
end
else
begin
Prescaler <= Prescaler + 1;
end
end
// if FastCount then
// Tick12 <= '1';
// end if;
end
endmodule
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