?? it51_alu.v
字號(hào):
//-----------------------------------------------------------------------------
// IT51 (Improved-T51) --
// --
// VERSION: 030723 --
// --
// Contact: yfchen58@gmail.com --
// --
//-----------------------------------------------------------------------------
// --
// IT51 - Improved T51 (VHDL 1-Cycle 8051 Compatible Microcontroller) --
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org) --
// Yung-Fu Chen (yfchen58@ms49.hinet.net) --
// --
//-----------------------------------------------------------------------------
// FETURE --
// . IT51_top interface is similar to synopsys DW8051 --
// . High-Performance 1-Cycle 8051 --
// . instruction compatible with standard DW8051 --
// . 256 byte internal data memory --
// . up to 64KB external data memory --
// . up to 64KB internal program memory --
// . export sfr-bus --
// . no dual-port memory used --
// . no watch-dog timer --
// . dual DPTR (DPTR0, DPTR1), refer to DW8051 --
// . sleep mode support, refer to DW8051 --
// . no stop mode --
// . six external interrupt, refer to DW8051 --
// . pass all DW8051 test-pattern --
// . UART/Timer are not fully tested yet --
// . no internal tri-state bus --
// . 2-Cycle MUL Instruction --
// --
//-----------------------------------------------------------------------------
// --
// IT51_top (Interface Compatible with Synopsys DW8051) --
// | --
// +-- IT51_core (Control Unit) --
// | | --
// | +-- IT51_ALU (ALU) --
// | | --
// | +-- IT51_MD (MUL/DIV) --
// | --
// +-- IT51_Glue (Glue Logic) --
// | --
// +-- IT51_TC01 (Timer/Counter-1) --
// | --
// +-- IT51_TC2 (Timer/Counter-2) --
// | --
// +-- IT51_UART (UART) --
// --
//-----------------------------------------------------------------------------
// ============================================================================
// The original T51 license is listed below:
// ============================================================================
//
// 8051 compatible microcontroller core
//
// Version : 0218
//
// Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Please report bugs to the author, but before you do so, please
// make sure that this is not a derivative work and that
// you have the latest version of this file.
//
// The latest version of this file can be found at:
// http://www.opencores.org/cvsweb.shtml/t51/
//
// Limitations :
//
// File history :
//
// ============================================================================
module IT51_ALU (Clk, Rst_n, Last, PCPause, OpCode, ACC, B, IA, IB, Bit_Pattern, CY_In, AC_In, ACC_Q, B_Q, IDCPBL_Q, Div_Rdy, CJNE, DJNZ, CY_Out, AC_Out, OV_Out, CY_Wr, AC_Wr, OV_Wr);
// included from package it51_pack
input Clk;
input Rst_n;
input Last;
input PCPause;
input[7:0] OpCode;
input[7:0] ACC;
input[7:0] B;
input[7:0] IA;
input[7:0] IB;
input[7:0] Bit_Pattern;
input CY_In;
input AC_In;
output[7:0] ACC_Q;
wire[7:0] ACC_Q;
output[7:0] B_Q;
wire[7:0] B_Q;
output[7:0] IDCPBL_Q;
reg[7:0] IDCPBL_Q;
output Div_Rdy;
wire Div_Rdy;
output CJNE;
wire CJNE;
output DJNZ;
wire DJNZ;
output CY_Out;
wire CY_Out;
output AC_Out;
wire AC_Out;
output OV_Out;
wire OV_Out;
output CY_Wr;
wire CY_Wr;
output AC_Wr;
wire AC_Wr;
output OV_Wr;
wire OV_Wr;
reg Do_A_Imm;
reg Do_A_Carry;
reg Do_A_RR;
reg Do_A_INC;
reg Do_A_RRC;
reg Do_A_DEC;
reg Do_A_RL;
reg Do_A_ADD;
reg Do_A_RLC;
reg Do_A_ORL;
reg Do_A_ANL;
reg Do_A_XRL;
reg Do_A_MOV;
reg Do_A_DIV;
reg Do_A_SUBB;
reg Do_A_MUL;
reg Do_A_CJNE;
reg Do_A_SWAP;
reg Do_A_XCH;
reg Do_A_DA;
reg Do_A_XCHD;
reg Do_A_CLR;
reg Do_A_CPL;
// Accumulator ALU input mux
wire[7:0] AOP2;
// AD intermediate signal
reg[8:0] ADA;
// AddSub intermediate signals
wire AS_Carry7;
wire AS_AC;
wire AS_CY;
wire[7:0] AS_Q;
reg Do_I_Imm;
reg Do_I_INC;
reg Do_I_DEC;
reg Do_I_ORL;
reg Do_I_ANL;
reg Do_I_XRL;
reg Do_I_MOV;
reg Do_I_MOVD;
reg Do_I_CJNE;
// Auxiliary ALU input mux
wire[7:0] IOP;
// Auxiliary ALU delayed input
reg[7:0] IA_d;
// AddSub intermediate signals
wire CJNE_CY_n;
wire[7:0] CJNE_Q;
// MOV intermediate signals
reg[3:0] MOV_Op;
reg[7:0] MOV_Q;
reg Do_B_Inv;
reg Do_B_C_BA;
reg Do_B_C_Dir;
reg Do_B_BA_Dir;
reg Do_B_MOV;
reg Do_B_JBC;
reg[1:0] Do_B_Op;
// Bit intermediate signals
wire[7:0] Bit_Op1;
wire[7:0] Bit_Op2;
wire Bit_IsOne;
wire[7:0] Bit_Result;
reg Last_r;
// MulDiv intermediate signals
wire[15:0] Mul_Q;
wire Mul_OV;
wire[15:0] Div_Q;
wire Div_OV;
//
wire[7:0] ACC_Q_0;
wire[7:0] ACC_Q_1;
wire[7:0] ACC_Q_2;
wire[7:0] ACC_Q_3;
wire[7:0] ACC_Q_4;
wire[7:0] ACC_Q_5;
wire[7:0] ACC_Q_6;
wire[7:0] ACC_Q_7;
wire[7:0] ACC_Q_8;
wire[7:0] ACC_Q_9;
wire[7:0] ACC_Q_10;
wire[7:0] ACC_Q_11;
wire[7:0] ACC_Q_12;
wire[7:0] ACC_Q_13;
wire[7:0] ACC_Q_14;
wire[7:0] ACC_Q_15;
wire[7:0] ACC_Q_16;
wire[7:0] ACC_Q_17;
wire[7:0] ACC_Q_18;
wire[7:0] ACC_Q_19;
// Simplify some of the conditions, not all must be exclusive !!!!
always @(posedge Clk or negedge Rst_n)
begin
if (Rst_n == 1'b0)
begin
Do_A_Imm <= 1'b0 ;
Do_A_Carry <= 1'b0 ;
Do_A_RR <= 1'b0 ;
Do_A_INC <= 1'b0 ;
Do_A_RRC <= 1'b0 ;
Do_A_DEC <= 1'b0 ;
Do_A_RL <= 1'b0 ;
Do_A_ADD <= 1'b0 ;
Do_A_RLC <= 1'b0 ;
Do_A_ORL <= 1'b0 ;
Do_A_ANL <= 1'b0 ;
Do_A_XRL <= 1'b0 ;
Do_A_MOV <= 1'b0 ;
Do_A_DIV <= 1'b0 ;
Do_A_SUBB <= 1'b0 ;
Do_A_MUL <= 1'b0 ;
Do_A_CJNE <= 1'b0 ;
Do_A_SWAP <= 1'b0 ;
Do_A_XCH <= 1'b0 ;
Do_A_DA <= 1'b0 ;
Do_A_XCHD <= 1'b0 ;
Do_A_CLR <= 1'b0 ;
Do_A_CPL <= 1'b0 ;
//Do_A_Imm <= 1'b0 ;
Do_I_Imm <= 1'b0 ;
Do_I_INC <= 1'b0 ;
Do_I_DEC <= 1'b0 ;
Do_I_ORL <= 1'b0 ;
Do_I_ANL <= 1'b0 ;
Do_I_XRL <= 1'b0 ;
Do_I_MOV <= 1'b0 ;
Do_I_MOVD <= 1'b0 ;
Do_I_CJNE <= 1'b0 ;
IA_d <= {8{1'b0}} ;
MOV_Op <= {4{1'b0}} ;
Do_B_Inv <= 1'b0 ;
Do_B_C_BA <= 1'b0 ;
Do_B_C_Dir <= 1'b0 ;
Do_B_BA_Dir <= 1'b0 ;
Do_B_MOV <= 1'b0 ;
Do_B_JBC <= 1'b0 ;
Do_B_Op <= {2{1'b0}} ;
Last_r <= 1'b0 ;
end
else
begin
// ACC Operations
Do_A_Imm <= 1'b0 ;
Do_A_Carry <= 1'b0 ;
Do_A_RR <= 1'b0 ;
Do_A_INC <= 1'b0 ;
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