{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 22 15:57:16 2006 " "Info: Processing started: Fri Sep 22 15:57:16 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off f_adder -c f_adder --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off f_adder -c f_adder --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../h_adder/h_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../h_adder/h_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 h_adder-ex1 " "Info: Found design unit 1: h_adder-ex1" {  } { { "../h_adder/h_adder.vhd" "" { Text "E:/JACK/VHDL/h_adder/h_adder.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 h_adder " "Info: Found entity 1: h_adder" {  } { { "../h_adder/h_adder.vhd" "" { Text "E:/JACK/VHDL/h_adder/h_adder.vhd" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../ior2/ior2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../ior2/ior2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ior2-ex2 " "Info: Found design unit 1: ior2-ex2" {  } { { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ior2 " "Info: Found entity 1: ior2" {  } { { "../ior2/ior2.vhd" "" { Text "E:/JACK/VHDL/ior2/ior2.vhd" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file f_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 f_adder-ex3 " "Info: Found design unit 1: f_adder-ex3" {  } { { "f_adder.vhd" "" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 6 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 f_adder " "Info: Found entity 1: f_adder" {  } { { "f_adder.vhd" "" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "f_adder " "Info: Elaborating entity \"f_adder\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "h_adder h_adder:m0 " "Info: Elaborating entity \"h_adder\" for hierarchy \"h_adder:m0\"" {  } { { "f_adder.vhd" "m0" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 17 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ior2 ior2:m2 " "Info: Elaborating entity \"ior2\" for hierarchy \"ior2:m2\"" {  } { { "f_adder.vhd" "m2" { Text "E:/JACK/VHDL/f_adder/f_adder.vhd" 19 -1 0 } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 22 15:57:17 2006 " "Info: Processing ended: Fri Sep 22 15:57:17 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}