; cout ; Output   ; --            ; --            ; --                    ; --  ;
+------+----------+---------------+---------------+-----------------------+-----+


+------------------------------------------------------+
; Pad To Core Delay Chain Fanout                       ;
+------------------------+-------------------+---------+
; Source Pin / Fanout    ; Pad To Core Index ; Setting ;
+------------------------+-------------------+---------+
; cin                    ;                   ;         ;
;      - h_adder:m1|r~14 ; 1                 ; ON      ;
;      - ior2:m2|z~67    ; 1                 ; ON      ;
; bin                    ;                   ;         ;
;      - h_adder:m1|r~14 ; 0                 ; ON      ;
;      - ior2:m2|z~67    ; 0                 ; ON      ;
; ain                    ;                   ;         ;
;      - h_adder:m1|r~14 ; 0                 ; ON      ;
;      - ior2:m2|z~67    ; 0                 ; ON      ;
+------------------------+-------------------+---------+


+---------------------------------+
; Non-Global High Fan-Out Signals ;
+-----------------+---------------+
; Name            ; Fan-Out       ;
+-----------------+---------------+
; ain             ; 2             ;
; bin             ; 2             ;
; cin             ; 2             ;
; ior2:m2|z~67    ; 1             ;
; h_adder:m1|r~14 ; 1             ;
+-----------------+---------------+


+---------------------------------------------------+
; Interconnect Usage Summary                        ;
+----------------------------+----------------------+
; Interconnect Resource Type ; Usage                ;
+----------------------------+----------------------+
; C4s                        ; 3 / 16,320 ( < 1 % ) ;
; Direct links               ; 0 / 21,944 ( 0 % )   ;
; Global clocks              ; 0 / 8 ( 0 % )        ;
; LAB clocks                 ; 0 / 240 ( 0 % )      ;
; LUT chains                 ; 0 / 5,382 ( 0 % )    ;
; Local interconnects        ; 5 / 21,944 ( < 1 % ) ;
; M4K buffers                ; 0 / 720 ( 0 % )      ;
; R4s                        ; 0 / 14,640 ( 0 % )   ;
+----------------------------+----------------------+


+--------------------------------------------------------------------------+
; LAB Logic Elements                                                       ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+--------------------------------------------+-----------------------------+
; 1                                          ; 0                           ;
; 2                                          ; 1                           ;
; 3                                          ; 0                           ;
; 4                                          ; 0                           ;
; 5                                          ; 0                           ;
; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 0                           ;
; 9                                          ; 0                           ;
; 10                                         ; 0                           ;
+--------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 2.00) ; Number of LABs  (Total = 1) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 0                           ;
; 2                                               ; 1                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 3.00) ; Number of LABs  (Total = 1) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 0                           ;
; 3                                           ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Sep 22 15:56:48 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off f_adder -c f_adder
Info: Selected device EP1C6Q240C8 for design "f_adder"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. 
    Info: Device EP1C12Q240C8 is compatible
Info: No exact pin location assignment(s) for 5 pins of 5 total pins
    Info: Pin rout not assigned to an exact location on the device
    Info: Pin cout not assigned to an exact location on the device
    Info: Pin cin not assigned to an exact location on the device
    Info: Pin bin not assigned to an exact location on the device
    Info: Pin ain not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1 MHz
    Info: Not setting a global tsu requirement
    Info: Not setting a global tco requirement
    Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 5 (unused VREF, 3.30 VCCIO, 3 input, 2 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  42 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
        Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  45 pins available
        Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Fri Sep 22 15:56:51 2006
    Info: Elapsed time: 00:00:03