entity b8_adder is
	port(c_1,a0,b0,a1,b1,a2,b2,a3,b3,a4,b4,a5,b5,a6,b6,a7,b7:in bit;
		r0,r1,r2,r3,r4,r5,r6,r7,c7:out bit);
end b8_adder;

architecture ex4 of b8_adder is
	component f_adder
		port(ain,bin,cin:in bit;
			rout,cout:out bit);
	end component;
	signal l,m,n,o,p,q,s:bit;
	begin
		mo:f_adder port map(cin=>c_1,ain=>a0,bin=>b0,rout=>r0,cout=>l);
		m1:f_adder port map(cin=>l,ain=>a1,bin=>b1,rout=>r1,cout=>m);
		m2:f_adder port map(cin=>m,ain=>a2,bin=>b2,rout=>r2,cout=>n);
		m3:f_adder port map(cin=>n,ain=>a3,bin=>b3,rout=>r3,cout=>o);
		m4:f_adder port map(cin=>o,ain=>a4,bin=>b4,rout=>r4,cout=>p);
		m5:f_adder port map(cin=>p,ain=>a5,bin=>b5,rout=>r5,cout=>q);
		m6:f_adder port map(cin=>q,ain=>a6,bin=>b6,rout=>r6,cout=>s);
		m7:f_adder port map(cin=>s,ain=>a7,bin=>b7,rout=>r7,cout=>c7);
end ex4;