module controller(clk1,clk2,n,OE);  //全加器模塊input clk1,clk2;  //定義clk1、clk2output [3:0] n; //定義輸出的控制信號noutput OE;     //定義輸出的控制信號OEreg [3:0] n,nextn;  //定義寄存器型狀態轉換變量變量reg OE;wire p;reg t,m;       //定義中間變量   assign p=!t&clk1;     //通過clk2采樣clk1，當上一周期采到低電平且下一周期采到高電平即上升延時，將控制信號n置零always@(posedge clk2)   begin     t=clk1;     if(p) n=0;     else n=nextn;   endalways@(n)         //當clk2來時，通過改變nextn的狀態來改變n的狀態，從而進行控制  begin       case(n)           0:   begin  OE=1; nextn=1; end           1:   begin  OE=0; nextn=2; end           2:   begin  OE=0; nextn=3; end           3:   begin  OE=0; nextn=4; end           4:   begin  OE=0; nextn=5; end           5:   begin  OE=0; nextn=6; end           6:   begin  OE=0; nextn=7; end           7:   begin  OE=0; nextn=8; end           8:   begin  OE=0; nextn=9; end           9:   begin  OE=0; nextn=0; end           default: begin  OE=0; nextn=0; end       endcase   endendmodule