/******************************************************************************
*
*  LOGIC CORE:          Command module			
*  MODULE NAME:         command()
*  COMPANY:             Northwest Logic Design, Inc.
*                       www.nwlogic.com
*
*  REVISION HISTORY:  
*
*    Revision 1.0  05/11/2000     Description: Initial Release.
*             1.1  07/10/2000     Description: change precharge to terminate
*                                              for full page accesses.
*
*  FUNCTIONAL DESCRIPTION:
*
*  This module is the command processor module for the SDR SDRAM controller.
*
*  Copyright Northwest Logic, Inc., 2000.  All rights reserved.  
******************************************************************************/


/*The command module accepts decoded commands from the control interface module, refresh requests from the
refresh control logic, and generates the appropriate commands to the SDRAM. The module contains a simple arbiter
that arbitrates between the commands from the host interface and the refresh requests from the refresh control logic.
The refresh requests from the refresh control logic have priority over the commands from the host interface. If a com-
mand from the host arrives at the same time or during a hidden refresh operation, the arbiter holds off the host by not
asserting CMDACK until the hidden refresh operation is complete. If a hidden refresh command is received while a
host operation is in progress, the hidden refresh is held off until the host operation is complete.
*/
module command(
        CLK,
        RESET_N,
        SADDR,
        NOP,
        READA,
        WRITEA,
        REFRESH,
        PRECHARGE,
        LOAD_MODE,
        SC_CL,
        SC_RC,
        SC_RRD,
        SC_PM,
        SC_BL,
        REF_REQ,
        REF_ACK,
        CM_ACK,
        OE,
        SA,
        BA,
        CS_N,
        CKE,
        RAS_N,
        CAS_N,
        WE_N
        );

`include        "params.v"

input                           CLK;                    // System Clock   模塊的系統(tǒng)時(shí)鐘
input                           RESET_N;                // System Reset   模塊復(fù)位信號(hào)
input   [`ASIZE-1:0]            SADDR;                  // Address        地址輸入（從control_interface模塊輸入）
input                           NOP;                    // Decoded NOP command                  解碼后的NOP命令（從control_interface模塊輸入）
input                           READA;                  // Decoded READA command                解碼后的READA命令（從control_interface模塊輸入）
input                           WRITEA;                 // Decoded WRITEA command               解碼后的WRITEA命令（從control_interface模塊輸入）
input                           REFRESH;                // Decoded REFRESH command              解碼后的REFRESH命令（從control_interface模塊輸入）
input                           PRECHARGE;              // Decoded PRECHARGE command            解碼后的PRECHARGE命令（從control_interface模塊輸入）
input                           LOAD_MODE;              // Decoded LOAD_MODE command            解碼后的LOAD_MODE命令（從control_interface模塊輸入）
input   [1:0]                   SC_CL;                  // Programmed CAS latency               編程的CAS傳輸延遲（從control_interface模塊輸入）
input   [1:0]                   SC_RC;                  // Programmed RC delay                  編程的RAS to CAS Delay（從control_interface模塊輸入）
input   [3:0]                   SC_RRD;                 // Programmed RRD delay                 編程的RRD延遲（從control_interface模塊輸入）
input                           SC_PM;                  // programmed Page Mode                 編程的Page Mode（從control_interface模塊輸入）
input   [3:0]                   SC_BL;                  // Programmed burst length              編程的burst length（從control_interface模塊輸入）
input                           REF_REQ;                // Hidden refresh request               隱藏的刷新請(qǐng)求信號(hào)（從control_interface模塊輸入）
output                          REF_ACK;                // Refresh request acknowledge          刷新請(qǐng)求確認(rèn)信號(hào)（輸出給control_interface模塊）
output                          CM_ACK;                 // Command acknowledge                  命令確認(rèn)信號(hào)（輸出給control_interface模塊）
output                          OE;                     // OE signal for data path module       輸出使能信號(hào)（輸出給data path module）
output  [11:0]                  SA;                     // SDRAM address                        SDRAM地址輸出，輸出給頂層模塊sdr_sdram           
output  [1:0]                   BA;                     // SDRAM bank address                   SDRAM bank選擇輸出，輸出給頂層模塊sdr_sdram
output  [1:0]                   CS_N;                   // SDRAM chip selects                   SDRAM 片選信號(hào)輸出，輸出給頂層模塊sdr_sdram
output                          CKE;                    // SDRAM clock enable                   SDRAM 時(shí)鐘使能輸出，輸出給頂層模塊sdr_sdram
output                          RAS_N;                  // SDRAM RAS                            SDRAM 行地址選通輸出，輸出給頂層模塊sdr_sdram
output                          CAS_N;                  // SDRAM CAS                            SDRAM 列地址選通輸出，輸出給頂層模塊sdr_sdram
output                          WE_N;                   // SDRAM WE_N                           SDRAM 寫操作使能輸出，輸出給頂層模塊sdr_sdram

            
reg                             CM_ACK;
reg                             REF_ACK;
reg                             OE;
reg     [11:0]                  SA;
reg     [1:0]                   BA;
reg     [1:0]                   CS_N;
reg                             CKE;
reg                             RAS_N;
reg                             CAS_N;
reg                             WE_N;



// Internal signals
reg                             do_nop;
reg                             do_reada;
reg                             do_writea;
reg                             do_writea1;
reg                             do_refresh;
reg                             do_precharge;
reg                             do_load_mode;            //內(nèi)部命令信號(hào)，在接收到control_interface模塊輸入的命令之后，如果SDRAM空閑，則這些內(nèi)部命令信號(hào)有效
reg                             command_done;            //標(biāo)志SDRAM正在運(yùn)行命令的信號(hào)，1表示命令正在運(yùn)行，0表示空閑
reg     [7:0]                   command_delay;           //命令延遲移位寄存器，確保SDRAM有足夠時(shí)間完成上一個(gè)命令操作
reg     [3:0]                   rw_shift;                //讀寫移位寄存器，用于跟蹤ACTIVATE命令和接下來的WRITEA or READA命令之間的間隔時(shí)間
reg                             do_act;                  //？？
reg                             rw_flag;                 //讀寫標(biāo)志，用于得到寫使能信號(hào)WE_N（僅用于讀寫命令中獲得WE_N，其他命令中的WE_N不用該標(biāo)志信號(hào)得出）
reg                             do_rw;                   //內(nèi)部讀寫觸發(fā)信號(hào)，1表示可觸發(fā)一次讀寫操作，0表示尚不能觸發(fā)讀寫操作
reg     [7:0]                   oe_shift;                //輸出使能信號(hào)移位寄存器
reg                             oe1;
reg                             oe2;
reg                             oe3;
reg                             oe4;                     //這4個(gè)信號(hào)用于逐級(jí)緩存ACTIVATE命令執(zhí)行時(shí)產(chǎn)生的輸出使能信號(hào)oe1，根據(jù)RAS to CAS Delay對(duì)其進(jìn)行延遲，使得WRITE命令有效時(shí)，OE有效，從而要寫入SDRAM中的數(shù)據(jù)能同時(shí)出現(xiàn)在數(shù)據(jù)總線上。當(dāng)進(jìn)行寫命令時(shí)，首先執(zhí)行ACTIVATE命令，行地址有效，激活相應(yīng)的行；然后經(jīng)過RAS to CAS Delay（從行地址有效到列地址有效的延遲時(shí)間）個(gè)時(shí)鐘周期，執(zhí)行寫命令，列地址有效。由于所寫的數(shù)據(jù)與寫命令要同時(shí)出現(xiàn)，即在列地址有效時(shí)數(shù)據(jù)必須出現(xiàn)在數(shù)據(jù)總線上，因此必須將輸出使能信號(hào)與寫命令對(duì)齊，即當(dāng)ACTIVATE命令執(zhí)行后，延遲RAS to CAS Delay個(gè)時(shí)鐘周期，給出輸出使能信號(hào)oe，保證數(shù)據(jù)能及時(shí)出現(xiàn)在數(shù)據(jù)總線上。
reg     [3:0]                   rp_shift;                //附加的移位寄存器，用于讀、寫、刷新命令，使SDRAM有足夠時(shí)間完成上一個(gè)讀、寫、刷新命令操作
reg                             rp_done;                 //標(biāo)志SDRAM正在繼續(xù)運(yùn)行讀、寫、刷新命令的信號(hào)，1表示命令正在繼續(xù)運(yùn)行，0表示空閑

wire    [`ROWSIZE - 1:0]        rowaddr;                 //內(nèi)部wire型變量，用于接收從control_interface模塊輸入的行地址信號(hào)
wire    [`COLSIZE - 1:0]        coladdr;                 //內(nèi)部wire型變量，用于接收從control_interface模塊輸入的列地址信號(hào)
wire    [`BANKSIZE - 1:0]       bankaddr;                //內(nèi)部wire型變量，用于接收從control_interface模塊輸入的bank選擇地址信號(hào)

assign   rowaddr   = SADDR[`ROWSTART + `ROWSIZE - 1: `ROWSTART];          // assignment of the row address bits from SADDR獲得行地址
assign   coladdr   = SADDR[`COLSTART + `COLSIZE - 1:`COLSTART];           // assignment of the column address bits from SADDR獲得列地址
assign   bankaddr  = SADDR[`BANKSTART + `BANKSIZE - 1:`BANKSTART];        // assignment of the bank address bits from SADDR獲得bank選擇地址



// This always block monitors the individual command lines and issues a command
// to the next stage if there currently another command already running.
//這個(gè)always塊監(jiān)測(cè)獨(dú)立的命令線，如果已有命令在運(yùn)行，則將新的命令推后執(zhí)行（時(shí)鐘信號(hào)CLK上升沿)
always @(posedge CLK or negedge RESET_N)
begin
        if (RESET_N == 0)                                                 //復(fù)位將命令信號(hào)和命令延遲移位寄存器、附加寄存器、SDRAM忙標(biāo)志等都清0
        begin
                do_nop          <= 0;
                do_reada        <= 0;
                do_writea       <= 0;
                do_refresh      <= 0;
                do_precharge    <= 0;
                do_load_mode    <= 0;
                command_done    <= 0;
                command_delay   <= 0;
                rw_flag         <= 0;
                rp_shift        <= 0;
                rp_done         <= 0;
        end
        
        else
        begin