------------------------------------------------------------------------------- Entity:      pcitb_stimgen-- File:        pcitb_stimgen.vhd-- Author:      Alf Vaerneus, Gaisler Research-- Description: PCI Stimuli generator. Contains the test sequence.------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.stdlib.all;library gaisler;use gaisler.ambatest.all;use gaisler.pcitb.all;use gaisler.ahb_tb.all;use gaisler.pci_tb.all;--LIBRARY adpms_lib;--USE adpms_lib.TEXTIO.ALL;entity pcitb_stimgen is  generic(    slots : integer := 5;    dbglevel : integer := 1);  port(    rsttrig   : out std_logic;    tbi       : out tbi_array_type;    tbo       : in  tbo_array_type      );end pcitb_stimgen;architecture tb of pcitb_stimgen isconstant zero32 : std_logic_vector(31 downto 0) := (others => '0');constant one32 : std_logic_vector(31 downto 0) := (others => '1');type config_array_type is array(0 to slots-1) of config_header_type;begin  test_sequence : process  variable ctrl : ctrl_type;  variable i : integer;  variable slotconf : config_array_type;  begin    ctrl := ctrl_init;    -- Reset system    rsttrig <= '0';    wait for 30 ns;    rsttrig <= '1';    wait for 30 ns;    rsttrig <= '0';    wait for 2 us;    printf(" ");    printf("-------------------------------");    printf("Simulation Start");    printf(" ");    ctrl.wfile := "pci_read.log      ";    ctrl.usewfile := true;    ctrl.userfile := false;    -- Configure existing PCI units    for i in 0 to slots-1 loop      ctrl.address := (others => '0');      ctrl.address((32-slots)+i) := '1';      printf("Scanning slot %d",i);      PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);      if ctrl.status = OK then        printf("Device found with ID %x",ctrl.data);        slotconf(i).devid := ctrl.data(31 downto 16);        slotconf(i).vendid := ctrl.data(15 downto 0);        ctrl.address(7 downto 2) := conv_std_logic_vector(1,6);        ctrl.data := (others => '1');        PCI_write_config(ctrl,tbi(0),tbo(0),dbglevel);        PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);        slotconf(i).status  := ctrl.data(31 downto 16);        slotconf(i).command := ctrl.data(15 downto 0);        ctrl.address(7 downto 2) := conv_std_logic_vector(2,6);        PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);        slotconf(i).class_code := ctrl.data(31 downto 8);        slotconf(i).revid := ctrl.data(7 downto 0);        ctrl.address(7 downto 2) := conv_std_logic_vector(3,6);        ctrl.data := (others => '1');        PCI_write_config(ctrl,tbi(0),tbo(0),dbglevel);        PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);        slotconf(i).bist := ctrl.data(31 downto 24);        slotconf(i).header_type := ctrl.data(23 downto 16);        slotconf(i).lat_timer := ctrl.data(15 downto 8);        slotconf(i).cache_lsize := ctrl.data(7 downto 0);        for j in 0 to 5 loop          ctrl.address(7 downto 2) := conv_std_logic_vector(j+4,6);          ctrl.data := (others => '1');          PCI_write_config(ctrl,tbi(0),tbo(0),dbglevel);          PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);          if ctrl.data > zero32 then            ctrl.data := (others => '0');            ctrl.data(31 downto 29) := conv_std_logic_vector(i,3);            ctrl.data(28 downto 26) := conv_std_logic_vector(j,3);            PCI_write_config(ctrl,tbi(0),tbo(0),dbglevel);            PCI_read_config(ctrl,tbi(0),tbo(0),dbglevel);            slotconf(i).bar(j) := ctrl.data;            printf("BAR%d",j);            printf("%x",ctrl.data);          end if;        end loop;      else        printf("No device found on slot %d",i);        slotconf(i).vendid := (others => '1');      end if;    end loop;    wait for 100 us;    printf(" ");    printf("-------------------------------");    printf(" ");    printf("Testcase 1: Read from target.");    printf(" ");    -- Try to read from every unit    for i in 0 to slots-1 loop      if slotconf(i).vendid /= one32(15 downto 0) then        ctrl.address := slotconf(i).bar(0);        ctrl.no_words := 8;        printf("Try to read from slot%d",i);        PCI_read_burst(ctrl,tbi(0),tbo(0),dbglevel);        if ctrl.status = OK then          printf("Read data %x",ctrl.data);        else          printf("Read failed!");        end if;      end if;    end loop;    wait for 5 us;    printf(" ");    printf("-------------------------------");    printf(" ");    printf("Testcase 2: Write to target and verify.");    printf(" ");    -- Try to read from every unit    for i in 0 to slots-1 loop      if slotconf(i).vendid /= one32(15 downto 0) then        ctrl.address := slotconf(i).bar(0);        ctrl.data := conv_std_logic_vector_signed(16#12345678#,32);        printf("Try to write to slot%d",i);        printf("Write data: %x",ctrl.data);        PCI_write_single(ctrl,tbi(0),tbo(0),dbglevel);        printf("Read and verify");        ctrl.usewfile := true;        ctrl.no_words := 8;        ctrl.wfile := "pci_read.log      ";        PCI_read_single(ctrl,tbi(0),tbo(0),dbglevel);        if ctrl.status = OK then          printf("Read data %x",ctrl.data);        else          printf("Read failed!");        end if;      end if;    end loop;    wait for 5 us;    printf(" ");    printf("-------------------------------");    printf(" ");    printf("Testcase 3: Write from file to target and verify.");    printf(" ");    ctrl.userfile := true;    -- Try to write from file    printf("Write data: %x",ctrl.data);    ctrl.rfile := "pcisequence.seq   ";    PCI_write_single(ctrl,tbi(0),tbo(0),dbglevel);    printf("Read and verify");    ctrl.rfile := "pcisequence2.seq  ";    PCI_read_single(ctrl,tbi(0),tbo(0),dbglevel);    if ctrl.status = OK then      printf("Read data %x",ctrl.data);    else      printf("Read failed!");    end if;    ctrl.userfile := false;    printf(" ");    printf("-------------------------------");    printf(" ");    printf("Testcase 4: Write from LEON to the PCI bus");    printf(" ");    ctrl.address := conv_std_logic_vector_signed(16#80100000#,32);    ctrl.data := conv_std_logic_vector_signed(16#F0000000#,32);    PCI_write_single(ctrl,tbi(0),tbo(0),dbglevel);    ctrl.address := conv_std_logic_vector_signed(16#80000000#,32);    ctrl.data := conv_std_logic_vector_signed(16#12345678#,32);    PCI_write_single(ctrl,tbi(0),tbo(0),dbglevel);    wait for 1 us;    ctrl.address := conv_std_logic_vector_signed(16#80000000#,32);    ctrl.data := conv_std_logic_vector_signed(16#12345678#,32);    ctrl.no_words := 2;    PCI_write_burst(ctrl,tbi(0),tbo(0),dbglevel);    wait for 1 us;    ctrl.address := conv_std_logic_vector_signed(16#80000000#,32);    ctrl.data := conv_std_logic_vector_signed(16#BADAAFFE#,32);    ctrl.no_words := 8;    PCI_write_burst(ctrl,tbi(0),tbo(0),dbglevel);    printf(" ");    printf("-------------------------------");    printf(" ");    printf("Testcase 5: Try DMA.");    printf(" ");    printf("DMA test 1: Read from local memory to a remote target on PCI.");    printf(" ");    printf("Running DMA test...");    printf(" ");    main_loop : for i in 2 to 33 loop      printf("Testing %d words.",i);      ctrl.address := conv_std_logic_vector_signed(16#8000050C#,32);      ctrl.data := conv_std_logic_vector(i,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000508#,32);      ctrl.data := conv_std_logic_vector(0,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000504#,32);      ctrl.data := conv_std_logic_vector_signed(16#40000000#,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000500#,32);      ctrl.data := conv_std_logic_vector_signed(16#00000087#,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      l2 : while true loop        ctrl.address := conv_std_logic_vector_signed(16#80000500#,32);        AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);        exit l2 when ctrl.data(2) = '1';        wait for 2 us;      end loop;      ctrl.address := conv_std_logic_vector_signed(16#00000000#,32);      ctrl.no_words := i;      ctrl.wfile := "file1.log         ";      PCI_read_burst(ctrl,tbi(0),tbo(0),dbglevel);      exit main_loop when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#40000000#,32);      ctrl.no_words := i;      ctrl.wfile := "file2.log         ";      AHB_read_burst(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop when ctrl.status /= OK;      printf("Compare data");      compfiles("file1.log         ","file2.log         ",1);    end loop;    printf("DMA test 2: Read from remote target on PCI to local memory.");    printf(" ");    printf("Preparing remote PCI target...");    printf(" ");    -- Try to write from file    printf("Write data: %x",ctrl.data);    ctrl.userfile := true;    ctrl.rfile := "pcisequence.seq   ";    PCI_write_burst(ctrl,tbi(0),tbo(0),dbglevel);    printf("Read and verify");    ctrl.address := conv_std_logic_vector_signed(16#00000000#,32);    ctrl.no_words := 45;    ctrl.userfile := false;    PCI_read_burst(ctrl,tbi(0),tbo(0),dbglevel);    if ctrl.status = OK then      printf("Read data %x",ctrl.data);    else      printf("Read failed!");    end if;    printf("Running DMA test...");    printf(" ");    main_loop2 : for i in 2 to 33 loop      printf("Testing %d words.",i);      ctrl.address := conv_std_logic_vector_signed(16#8000050C#,32);      ctrl.data := conv_std_logic_vector(i,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000508#,32);      ctrl.data := conv_std_logic_vector(0,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000504#,32);      ctrl.data := conv_std_logic_vector_signed(16#E0000000#,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#80000500#,32);      ctrl.data := conv_std_logic_vector_signed(16#00000085#,32);      AHB_write_single(ctrl,tbi(8),tbo(8),dbglevel);      exit main_loop2 when ctrl.status /= OK;      l1 : while true loop        ctrl.address := conv_std_logic_vector_signed(16#80000500#,32);        AHB_read_single(ctrl,tbi(8),tbo(8),dbglevel);        exit l1 when ctrl.data(2) = '1';        wait for 2 us;      end loop;      ctrl.address := conv_std_logic_vector_signed(16#00000000#,32);      ctrl.no_words := i;      ctrl.wfile := "file1.log         ";      PCI_read_burst(ctrl,tbi(0),tbo(0),dbglevel);      exit main_loop2 when ctrl.status /= OK;      ctrl.address := conv_std_logic_vector_signed(16#E0000000#,32);      ctrl.no_words := i;      ctrl.wfile := "file2.log         ";      AHB_read_burst(ctrl,tbi(9),tbo(9),dbglevel);      exit main_loop2 when ctrl.status /= OK;      printf("Compare data");      compfiles("file1.log         ","file2.log         ",1);    end loop;    printf(" ");    printf("Test: DMA done.");    printf(" ");    wait for 10 us;    printf(" ");    printf("-------------------------------");    printf("Simulation Complete");    printf(" ");    assert false      report "Simulation Finished"      severity failure;  end process;end;