------------------------------------------------------------------------------- Entity:      pci_top-- File:        pci_top.vhd-- Author:      Alf Vaerneus, Gaisler Research-- Description: PCI top module, that emulates a full PCI bus system------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library gaisler;use gaisler.pcitb.all;use gaisler.ambatest.all;library techmap;use techmap.gencomp.all; use gaisler.sim.all;entity pci_top is  generic(    slots : integer := 6;    nleon : integer := 5;    tresptime : integer := 1;    tlatency : integer := 0;    tbars : integer := 2;    trbuf : integer := 8;    tstopwd : boolean := true;    tval : time := 7 ns;    mhz66 : boolean := false;    bit64 : boolean := false;    dbglevel : integer := 1;    tech  : integer := atc18;    memtech : integer := memvirage;    disas : integer := 0    );end pci_top;architecture tb of pci_top isconstant rstclocks : integer := 20;constant sysctrl : boolean := true;component tbgen  generic (    ncpu      : integer := 1;		-- Number of CPU's    tech      : integer := 0;		-- target technology    memtech   : integer := 0;           -- memory technology     memtype   : integer := 0;   -- SDRAM = 1    pci       : integer := 0;    msg1      : string := "32 kbyte 32-bit rom, 0-ws";    msg2      : string := "2x128 kbyte 32-bit ram, 0-ws";    pcihost   : boolean := false;	-- be PCI host    DISAS     : integer := 0;	-- enable disassembly to stdout    clkperiod : integer := 45;		-- system clock period (ns)    promfile  : string := "prom.srec";  -- rom contents    sramfile  : string := "hello7.srec";  -- ram contents    sdramfile : string := "hello7.srec";  -- sdram contents    romwidth  : integer := 32;		-- rom data width (8/32)    romdepth  : integer := 13;		-- rom address depth    romtacc   : integer := 10;		-- rom access time (ns)    ramwidth  : integer := 32;		-- ram data width (8/16/32)    ramdepth  : integer := 15;		-- ram address depth    rambanks  : integer := 2;		-- number of ram banks    bytewrite : boolean := true;	-- individual byte write strobes    ramtacc   : integer := 10;		-- ram access time (ns)    blength   : integer := 4; -- DMA control burst length    fifodepth : integer := 3; -- Size of PCI interface buffer FIFO    pcimasteren : integer := 1; -- Enable PCI master functionality    pci_dev_id : integer := 0;    pci_vend_id : integer := 0  );  port (    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;  -- ignored in host bridge core    pci_lock    : inout std_ulogic;  -- Phoenix core: input only    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;    pci_req 	: inout std_ulogic;  -- tristate pad but never read    pci_serr    : inout std_ulogic;  -- open drain output    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic;    tbi : in tbi_array_type;    tbo : out tbo_array_type  );end component;signal pci : pci_type;signal rsttrig : std_logic;signal tbi : tbi_array_type;signal tbo : tbo_array_type;type nl_tbi_type is array(0 to 2*nleon) of tbi_array_type;type nl_tbo_type is array(0 to 2*nleon) of tbo_array_type;signal nltbi : nl_tbi_type;signal nltbo : nl_tbo_type;begin  pci <= pci_idle;  clkgen : pcitb_clkgen  generic map(mhz66 => mhz66, rstclocks => rstclocks)  port map(rsttrig => rsttrig, systclk => pci.syst);  arbiter : pcitb_arb  generic map(slots => slots, tval => tval)  port map(systclk => pci.syst, ifcin => pci.ifc, arbin => pci.arb, arbout => pci.arb);  monitor : pcitb_monitor  generic map(dbglevel => dbglevel)  port map(pciin => pci);  syshost : if sysctrl generate    master : pcitb_master    generic map(tval => tval, dbglevel => dbglevel)    port map(pciin => pci, pciout => pci, tbi => tbi(0), tbo => tbo(0));    target : pcitb_target    generic map(abits => 11, bars => tbars, resptime => tresptime,                latency => tlatency, rbuf => trbuf, stopwd => tstopwd, tval => tval, dbglevel => dbglevel)    port map(pciin => pci, pciout => pci, tbi => tbi(1), tbo => tbo(1));  end generate;  stimgen : pcitb_stimgen  generic map(slots => slots, dbglevel => dbglevel)  port map(rsttrig => rsttrig, tbi => tbi, tbo => tbo);  leon : for i in 1 to nleon generate    nltbi(i) <= (0 => tbi(2*i), 1 => tbi((2*i)+1), others => tb_in_init);    tbo(2*i) <= nltbo(i)(0); tbo((2*i)+1) <= nltbo(i)(1);    slotn : tbgen    generic map (memtype => 1, clkperiod => 30, promfile => "boot.srec", sramfile => "hello7.srec", tech => tech, DISAS => disas,      pci => 4, blength => 18, fifodepth => 4, pcimasteren => 1, pci_dev_id => 16#0213#+i, pci_vend_id => 16#16E4#, memtech => memtech)    port map (pci_rst => pci.syst.rst, pci_clk => pci.syst.clk, pci_gnt => pci.arb.gnt(i),              pci_idsel => pci.ifc.idsel(i), pci_lock => open, pci_ad => pci.ad.ad,              pci_cbe => pci.ad.cbe, pci_frame => pci.ifc.frame, pci_irdy => pci.ifc.irdy,              pci_trdy => pci.ifc.trdy, pci_devsel => pci.ifc.devsel, pci_stop => pci.ifc.stop,              pci_perr => pci.err.perr, pci_par => pci.ad.par, pci_req => pci.arb.req(i),              pci_serr => pci.err.serr, pci_host => 'H', pci_66 => '0',              tbi => nltbi(i), tbo => nltbo(i));  end generate;  nltbi(nleon+1) <= (0 => tbi((2*nleon)+2), 1 => tbi((2*nleon)+3), others => tb_in_init);  tbo((2*nleon)+2) <= nltbo(nleon+1)(0); tbo((2*nleon)+3) <= nltbo(nleon+1)(1);  leonmaster : tbgen  generic map (memtype => 1, clkperiod => 30, promfile => "boot.srec", sramfile => "hello7.srec", tech => tech, DISAS => disas,    pci => 4, blength => 18, fifodepth => 3, pcimasteren => 1, pci_dev_id => 16#0213#+nleon+1, pci_vend_id => 16#16E4#, memtech => memtech)    port map (pci_rst => pci.syst.rst, pci_clk => pci.syst.clk, pci_gnt => pci.arb.gnt(nleon+1),              pci_idsel => pci.ifc.idsel(nleon+1), pci_lock => open, pci_ad => pci.ad.ad,              pci_cbe => pci.ad.cbe, pci_frame => pci.ifc.frame, pci_irdy => pci.ifc.irdy,              pci_trdy => pci.ifc.trdy, pci_devsel => pci.ifc.devsel, pci_stop => pci.ifc.stop,              pci_perr => pci.err.perr, pci_par => pci.ad.par, pci_req => pci.arb.req(nleon+1),              pci_serr => pci.err.serr, pci_host => 'H', pci_66 => '0',              tbi => nltbi(nleon+1), tbo => nltbo(nleon+1));  pci.ifc.idsel(slots-1 downto 0) <= pci.ad.ad(31 downto (32-slots));  pci.ad.cbe <= buskeep(pci.ad.cbe), (others => 'L') after 25 ns;  pci.ad.ad <= buskeep(pci.ad.ad), (others => 'L') after 25 ns;  pci.ad.par <= buskeep(pci.ad.par), 'L' after 25 ns;end;