library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.amba.all;use grlib.stdlib.all;library techmap;use techmap.gencomp.all;library esa;use esa.memoryctrl.all;library gaisler;use gaisler.ambatest.all;use gaisler.memctrl.all;use gaisler.leon3.all;use gaisler.uart.all;use gaisler.misc.all;use gaisler.pci.all;entity leon3pci is  generic (    ncpu  : integer := 1;    tech  : integer := virtex2;    memtech : integer := virtex2;     memtype : integer := 0;    pci   : integer := 3;    disas : integer := 0;    blength : integer := 12;    fifodepth : integer := 8;    pcimasteren : integer := 1;    pci_dev_id : integer := 16#0214#;    pci_vend_id : integer := 16#16E4#;    clkper : time := 20 ns  );  port (    resetn	: in  std_ulogic;    clk	: in  std_ulogic;    pllref 	: in  std_ulogic;    errorn	: out std_ulogic;    address : out std_logic_vector(27 downto 0);    data	: inout std_logic_vector(31 downto 0);    sdclk  	: out std_ulogic;    sdcke  	: out std_logic_vector (1 downto 0);    -- sdram clock enable    sdcsn  	: out std_logic_vector (1 downto 0);    -- sdram chip select    sdwen  	: out std_ulogic;                       -- sdram write enable    sdrasn  : out std_ulogic;                       -- sdram ras    sdcasn  : out std_ulogic;                       -- sdram cas    sddqm   : out std_logic_vector (3 downto 0);    -- sdram dqm    dsutx  	: out std_ulogic; 			-- DSU tx data    dsurx  	: in  std_ulogic;  			-- DSU rx data    txd1   	: out std_ulogic; 			-- UART1 tx data    rxd1   	: in  std_ulogic;  			-- UART1 rx data    ramsn  	: out std_logic_vector (4 downto 0);    ramoen 	: out std_logic_vector (4 downto 0);    rwen   	: out std_logic_vector (3 downto 0);    oen    	: out std_ulogic;    writen 	: out std_ulogic;    read   	: out std_ulogic;    iosn   	: out std_ulogic;    romsn  	: out std_logic_vector (1 downto 0);    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;  -- ignored in host bridge core    pci_lock    : inout std_ulogic;  -- Phoenix core: input only    pci_ad    : inout std_logic_vector(31 downto 0);    pci_cbe   : inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy    : inout std_ulogic;    pci_trdy  : inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop  : inout std_ulogic;    pci_perr  : inout std_ulogic;    pci_par   : inout std_ulogic;    pci_req   : inout std_ulogic;  -- tristate pad but never read    pci_serr    : inout std_ulogic;  -- open drain output    pci_host    : in std_ulogic;    pci_66	: in std_ulogic;    tbi : in tbi_array_type;    tbo : out tbo_array_type	);end;architecture rtl of leon3pci isconstant FABTECH : integer := tech;constant pcitrc : integer := 1;constant oepol : integer := padoen_polarity(tech);signal memi : memory_in_type;signal memo : memory_out_type;signal wpo : wprot_out_type;signal sdi : sdctrl_in_type;signal sdo2 : sdctrl_out_type;signal sdo : sdram_out_type;signal apbi : apb_slv_in_type;signal apbo : apb_slv_out_vector := (others => apb_none);signal ahbsi, ahbsi2 : ahb_slv_in_type;signal ahbso : ahb_slv_out_vector := (others => ahbs_none);signal ahbso2 : ahb_slv_out_type;signal ahbmi : ahb_mst_in_type;signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);signal clkm, rstn, pciclk, sdclkl, rstraw, lclk : std_ulogic;signal cgi : clkgen_in_type;signal cgo : clkgen_out_type;signal u1i, dui : uart_in_type;signal u1o, duo : uart_out_type;signal gpti : gptimer_in_type;signal gpto : gptimer_out_type;signal dbgi : l3_debug_in_vector(0 to NCPU-1);signal dbgo : l3_debug_out_vector(0 to NCPU-1);signal irqi : irq_in_vector(0 to NCPU-1);signal irqo : irq_out_vector(0 to NCPU-1);signal pcii : pci_in_type;signal pcio : pci_out_type;signal gnd : std_logic;begin-------------------------------------------------------------------------  Reset and Clock generation  -----------------------------------------------------------------------------------------------------------  cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;  gnd <= '0';    clk_pad : clkpad generic map (tech => tech) port map (clk, lclk);       clkgen0 : clkgen  		-- clock generator  generic map (clk_mul => 2, clk_div => 2, sdramen => 1, tech => tech )  port map ( lclk, lclk, clkm, open, open, sdclk, pciclk, cgi, cgo);  rst0 : rstgen			-- reset generator  port map (resetn, clkm, cgo.clklock, rstn, rstraw);-------------------------------------------------------------------------  AHB CONTROLLER ------------------------------------------------------------------------------------------------------------------------  ahb0 : ahbctrl 		-- AHB arbiter/multiplexer  port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);-------------------------------------------------------------------------  AHB Masters  --------------------------------------------------------------------------------------------------------------------------  cpu : for i in 0 to NCPU-1 generate    u0 : leon3s			-- LEON3 processor    generic map (hindex => i, fabtech => FABTECH, memtech => memtech,	disas => disas, pclow => 0, icen => 1, dcen => 1)    port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,		irqi(i), irqo(i), dbgi(i), dbgo(i));  end generate;--  pci0 : pci_target generic map (ahbndx => NCPU)--  port map (rstn, rstn, clkm, clkm, pcii, pcio, ahbmi, ahbmo(NCPU));  pci_tg0 : if pci = 0 generate    pci : pci_target generic map (hindex => NCPU, device_id => pci_dev_id, vendor_id => pci_vend_id, oepol => oepol)    port map (rstn, clkm, pci_clk, pcii, pcio, ahbmi, ahbmo(NCPU));  end generate;  pci_mt0 : if pci = 1 generate    pci : pci_mt generic map (hmstndx => NCPU, hslvndx => 3, master => pcimasteren, device_id => pci_dev_id, vendor_id => pci_vend_id, oepol => oepol)    port map (rstn, clkm, pci_clk, pcii, pcio, ahbmi, ahbmo(NCPU), ahbsi, ahbso(3));  end generate;--  pci_oc0 : if pci = 2 generate--    pci : pci_oc generic map (mstndx => NCPU, slvndx => 2, device_id => pci_dev_id, vendor_id => pci_vend_id)--    port map (rstn, pci_rst, clkm, pci_clk, pcii, pcio, ahbmi, ahbmo(NCPU), ahbsi, ahbso(2));--  end generate;  pci_mtf0 : if pci = 3 generate    pci : pci_mtf generic map (memtech => memtech, hmstndx => NCPU, fifodepth => fifodepth, device_id => pci_dev_id, vendor_id => pci_vend_id,    master => pcimasteren, hslvndx => 3, pindex => 4, paddr => 4,  nsync => 1, oepol => oepol)    port map (rstn, clkm, pci_clk, pcii, pcio, apbi, apbo(4), ahbmi, ahbmo(NCPU), ahbsi, ahbso(3));  end generate;  pci_mtf1 : if pci = 4 generate    ahbmtb : ahbmst_em    generic map(hindex => NCPU+3,timeoutc => 300)    port map(rstn,clkm,ahbmi,ahbmo(NCPU+3),tbi(0),tbo(0));    ahbstb : ahbslv_em    generic map(hindex => 4, abits => 15, waitcycles => 2, retries => 0, memaddr => 16#E00#, memmask => 16#FFF#)    port map(rstn,clkm,ahbsi,ahbso(4),tbi(1),tbo(1));    dma : dmactrl generic map (hindex => NCPU+2, pindex => 5, paddr => 5, blength => blength)    port map (rstn, clkm, apbi, apbo(5), ahbmi, ahbmo(NCPU+2), ahbsi, ahbso(3), ahbsi2, ahbso2);    pci : pci_mtf generic map (memtech => memtech, hmstndx => NCPU, dmamst => NCPU+2, readpref => 1, fifodepth => fifodepth, device_id => pci_dev_id, vendor_id => pci_vend_id,    master => pcimasteren, hslvndx => 3, pindex => 4, paddr => 4,  nsync => 1, oepol => oepol)    port map (rstn, clkm, pci_clk, pcii, pcio, apbi, apbo(4), ahbmi, ahbmo(NCPU), ahbsi2, ahbso2);  end generate;  pci_dma : if pci = 5 generate -- master/target with fifo and DMA    pci : pcidma generic map (memtech => memtech, dmstndx => NCPU+2,     dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => NCPU,    fifodepth => fifodepth, device_id => pci_dev_id, vendor_id => pci_vend_id,    slvndx => 3, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#, nsync => 1)    port map (rstn, clkm, pci_clk, pcii, pcio, apbo(5), ahbmo(NCPU+2), apbi, apbo(4), ahbmi, ahbmo(NCPU), ahbsi, ahbso(3));  end generate;--  pci_dma : if pci = 5 generate--    pci : pci_mtf generic map (memtech => memtech, hmstndx => NCPU, fifodepth => fifodepth, device_id => pci_dev_id, vendor_id => pci_vend_id,--    master => pcimasteren, hslvndx => 3, pindex => 4, paddr => 4,  nsync => 1, oepol => oepol)--    port map (rstn, clkm, pci_clk, pcii, pcio, apbi, apbo(4), ahbmi, ahbmo(NCPU), ahbsi, ahbso(3));--  end generate;  pci_trc0 : if pcitrc /= 0 generate    pt0 : pcitrace generic map (depth => 10, memtech => memtech,  pindex  => 6, paddr => 16#100#, pmask => 16#f00#)      port map ( rstn, clkm, pci_clk, pcii, apbi, apbo(6));  end generate;  dcom0: ahbuart		-- Debug UART  generic map (hindex => NCPU+1, pindex => 7, paddr => 7)  port map (rstn, clkm, dui, duo, apbi, apbo(7),            ahbmi, ahbmo(NCPU+1));  dui.rxd <= dsurx; dsutx <= duo.txd;-------------------------------------------------------------------------  AHB Slaves   ----------------------------------------------------------------------------------------------------------------------------    sd0 : sdctrl                  -- SDRAM controller--    generic map (ahbndx => 0, memmask => 16#FF0#,--          ioaddr => 1, pwron => 1)--    port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);--  sd0 : mctrl 			-- LEON2 memory controller--  generic map (ahbndx => 0, apbndx => 0, memaddr => 0, apbaddr => 0, sden => 0)--  port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);--  dmasram : dmactrl generic map (mstndx => NCPU+2, apbndx => 5, apbaddr => 5, blength => blength)--  port map (rstn, clkm, apbi, apbo(5), ahbmi, ahbmo(NCPU+2), ahbsi, ahbso(0), ahbsi2, ahbso2);  mem0: if memtype = 0 generate    sr0 : srctrl 			-- LEON3 prom/sram memory controller    generic map (hindex => 0, romws => 2, rmw => 1)    port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo2);    sdo.sdcke <= sdo2.sdcke; sdo.sdcsn <= sdo2.sdcsn; sdo.sdwen <= sdo2.sdwen;    sdo.rasn <= sdo2.rasn; sdo.casn <= sdo2.casn; sdo.dqm <= sdo2.dqm;  end generate;  mem1: if memtype = 1 generate    sd0 : mctrl 			-- LEON2 memory controller    generic map (hindex => 0, pindex => 0, paddr => 0, fast => 0, sden => 1)      port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);  end generate;  apb0 : apbctrl			-- AHB/APB bridge  generic map (hindex => 1, haddr => 16#800#)  port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );  ahbram0 : ahbram generic map (hindex => 2, haddr => 16#D00#,   tech => memtech, kbytes => 16)  port map ( rstn, clkm, ahbsi, ahbso(2));-------------------------------------------------------------------------  APB Slaves  ---------------------------------------------------------------------------------------------------------------------------  uart0 : apbuart			-- UART 1  generic map (pindex => 1, paddr => 1,  pirq => 3, console => 1)  port map (rstn, clkm, apbi, apbo(1), u1i, u1o);  u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;  irqctrl0 : irqmp			-- interrupt controller  generic map (pindex => 2, paddr => 2, ncpu => NCPU)  port map (rstn, clkm, apbi, apbo(2), irqo, irqi);  timer0 : gptimer 			-- timer unit  generic map (pindex => 3, paddr => 3, pirq => 8, ntimers => 2, sepirq => 1)  port map (rstn, clkm, apbi, apbo(3), gpti, gpto);--------------------------------------------------------------------------  PADS  -----------------------------------------------------------------------------------------------------------------------------------  bdr : for i in 0 to 3 generate    data(31-i*8 downto 24-i*8) <= memo.data(31-i*8 downto 24-i*8)	when memo.bdrive(i) = '0' else (others => 'Z');  end generate;  memi.data <= data;  memi.brdyn <= '1'; memi.bexcn <= '1';  memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";  address <= memo.address(27 downto 0);  sdcke <= sdo.sdcke; sdwen <= sdo.sdwen;  sdcsn <= sdo.sdcsn; sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm(3 downto 0);--  sdsigs: if memtype = 1 generate--    sdi.data <= data; sdi.wprot <= '0';  --    sdcke <= sdo.sdcke; sdwen <= sdo.sdwen;--    sdcsn <= sdo.sdcsn; sdrasn <= sdo.rasn; sdcasn <= sdo.casn; sddqm <= sdo.dqm;--  end generate;  errorn <= '0' when dbgo(0).error = '0' else 'Z';  ramsn <= memo.ramsn(4 downto 0);  romsn <= memo.romsn(1 downto 0);  oen <= memo.oen;  rwen <= memo.wrn;  ramoen <= memo.ramoen(4 downto 0);  writen <= memo.writen;  read <= memo.read;  iosn <= memo.iosn;  pcipads0 : pcipads  generic map (padtech => tech, oepol => oepol)  port map (pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe, pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop,            pci_perr, pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio);--  pci_ad <= pcio.ad after 5 ns when pcio.aden = '0' else (others => 'Z') after 5 ns;--  pci_cbe(0) <= pcio.cbe(0) after 5 ns when pcio.cbeen(0) = '0' else 'Z' after 5 ns;--  pci_cbe(1) <= pcio.cbe(1) after 5 ns when pcio.cbeen(1) = '0' else 'Z' after 5 ns;--  pci_cbe(2) <= pcio.cbe(2) after 5 ns when pcio.cbeen(2) = '0' else 'Z' after 5 ns;--  pci_cbe(3) <= pcio.cbe(3) after 5 ns when pcio.cbeen(3) = '0' else 'Z' after 5 ns;--  pci_frame <= pcio.frame after 5 ns when pcio.frameen = '0' else 'Z' after 5 ns;--  pci_irdy <= pcio.irdy after 5 ns when pcio.irdyen = '0' else 'Z' after 5 ns;--  pci_trdy <= pcio.trdy after 5 ns when pcio.trdyen = '0' else 'Z' after 5 ns;--  pci_stop <= pcio.stop after 5 ns when pcio.stopen = '0' else 'Z' after 5 ns;--  pci_devsel <= pcio.devsel after 5 ns when pcio.devselen = '0' else 'Z' after 5 ns;--  pci_perr <= pcio.perr after 5 ns when pcio.perren = '0' else 'Z' after 5 ns;--  pci_par <= pcio.par after 5 ns when pcio.paren = '0' else 'Z' after 5 ns;--  pci_req <= pcio.req;--  pci_serr <= '0' after 5 ns when pcio.serren = '0' else 'Z' after 5 ns;--  pci_lock <= pcio.lock after 5 ns when pcio.locken = '0' else 'Z' after 5 ns;--  pcii.rst    	<= pci_rst;--  pcii.gnt    	<= pci_gnt;--  pcii.idsel 	<= pci_idsel;--  pcii.ad    	<= pci_ad;--  pcii.cbe   	<= pci_cbe;--  pcii.frame	<= pci_frame;--  pcii.irdy    	<= pci_irdy;--  pcii.trdy    	<= pci_trdy;--  pcii.devsel  	<= pci_devsel;--  pcii.stop    	<= pci_stop;--  pcii.lock    	<= pci_lock;--  pcii.perr    	<= pci_perr;--  pcii.serr    	<= pci_serr;--  pcii.par 	<= pci_par;--  pcii.host   	<= pci_host;--  pcii.pci66	<= pci_pci66;--  pcii.pme_status<= pci_pme_status;--------------------------------------------------------------------------  Boot message  ----------------------------------------------------------------------------------------------------------------------------- pragma translate_off  x : report_version  generic map (   msg1 => "LEON3 Demonstration design",   msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/100) & "." & tost((LIBVHDL_VERSION mod 10)/10)      & "." & tost(LIBVHDL_VERSION mod 100),   msg3 => "Target technology: " & tech_table(FABTECH) & ",  memory library: " & tech_table(memtech),   mdel => 1  );-- pragma translate_onend;