library ieee;use ieee.std_logic_1164.all;library techmap;use techmap.gencomp.all;library gaisler;use gaisler.ambatest.all;use gaisler.libdcom.all;use gaisler.sim.all;library micron;use micron.components.all;library work;entity tbgen is  generic (    ncpu      : integer := 1;		-- Number of CPU's    tech      : integer := 0;		-- target technology    memtech   : integer := 0;           -- memory technology    memtype   : integer := 0;   -- Type of memory, SRAM/SDRAM    pci       : integer := 0;		-- pci core    msg1      : string := "32 kbyte 32-bit rom, 0-ws";    msg2      : string := "2x128 kbyte 32-bit ram, 0-ws";    pcihost   : boolean := false;	-- be PCI host    DISAS     : integer := 0;	-- enable disassembly to stdout    clkperiod : integer := 20;		-- system clock period    promfile  : string := "prom.srec";  -- rom contents    sramfile  : string := "hello.srec";  -- ram contents    sdramfile : string := "hello.srec";  -- sdram contents    romwidth  : integer := 32;		-- rom data width (8/32)    romdepth  : integer := 13;		-- rom address depth    romtacc   : integer := 10;		-- rom access time (ns)    ramwidth  : integer := 32;		-- ram data width (8/16/32)    ramdepth  : integer := 15;		-- ram address depth    rambanks  : integer := 2;		-- number of ram banks    bytewrite : boolean := true;	-- individual byte write strobes    ramtacc   : integer := 10;		-- ram access time (ns)    blength   : integer := 4;    fifodepth : integer := 3;    pcimasteren : integer := 1;    pci_dev_id : integer := 0;    pci_vend_id : integer := 0  );  port (    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;  -- ignored in host bridge core    pci_lock    : inout std_ulogic;  -- Phoenix core: input only    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;    pci_req 	: inout std_ulogic;  -- tristate pad but never read    pci_serr    : inout std_ulogic;  -- open drain output    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic;    tbi : in tbi_array_type;    tbo : out tbo_array_type  );end;architecture behav of tbgen iscomponent leon3pci  generic (    ncpu  : integer := 1;    tech  : integer := 0;    memtech : integer := virtex2;     memtype : integer := 0;    pci   : integer := 0;    disas : integer := 0;    blength : integer := 4;    fifodepth : integer := 3;    pcimasteren : integer := 1;    pci_dev_id : integer := 0;    pci_vend_id : integer := 0;    clkper : time := 20 ns  );  port (	resetn	: in  std_ulogic;	clk	: in  std_ulogic;  	pllref 	: in  std_ulogic;	errorn	: out std_ulogic;	address : out std_logic_vector(27 downto 0);	data	: inout std_logic_vector(31 downto 0);  	sdclk  	: out std_ulogic;  	sdcke  	: out std_logic_vector (1 downto 0);    -- sdram clock enable  	sdcsn  	: out std_logic_vector (1 downto 0);    -- sdram chip select  	sdwen  	: out std_ulogic;                       -- sdram write enable  	sdrasn  : out std_ulogic;                       -- sdram ras  	sdcasn  : out std_ulogic;                       -- sdram cas  	sddqm   : out std_logic_vector (3 downto 0);    -- sdram dqm  	dsutx  	: out std_ulogic; 			-- DSU tx data  	dsurx  	: in  std_ulogic;  			-- DSU rx data  	txd1   	: out std_ulogic; 			-- UART1 tx data  	rxd1   	: in  std_ulogic;  			-- UART1 rx data  	ramsn  	: out std_logic_vector (4 downto 0);  	ramoen 	: out std_logic_vector (4 downto 0);  	rwen   	: out std_logic_vector (3 downto 0);  	oen    	: out std_ulogic;  	writen 	: out std_ulogic;  	read   	: out std_ulogic;  	iosn   	: out std_ulogic;  	romsn  	: out std_logic_vector (1 downto 0);    pci_rst     : in std_ulogic;		-- PCI bus    pci_clk 	: in std_ulogic;    pci_gnt     : in std_ulogic;    pci_idsel   : in std_ulogic;  -- ignored in host bridge core    pci_lock    : inout std_ulogic;  -- Phoenix core: input only    pci_ad 	: inout std_logic_vector(31 downto 0);    pci_cbe 	: inout std_logic_vector(3 downto 0);    pci_frame   : inout std_ulogic;    pci_irdy 	: inout std_ulogic;    pci_trdy 	: inout std_ulogic;    pci_devsel  : inout std_ulogic;    pci_stop 	: inout std_ulogic;    pci_perr 	: inout std_ulogic;    pci_par 	: inout std_ulogic;    pci_req 	: inout std_ulogic;  -- tristate pad but never read    pci_serr    : inout std_ulogic;  -- open drain output    pci_host   	: in std_ulogic;    pci_66	: in std_ulogic;    tbi : in tbi_array_type;    tbo : out tbo_array_type	);end component;signal clk : std_logic := '0';signal Rst    : std_logic := '0';			-- Resetconstant ct : integer := clkperiod/2;constant clkper : time := 20 ns;signal address  : std_logic_vector(27 downto 0);signal data     : std_logic_vector(31 downto 0);signal ramsn    : std_logic_vector(4 downto 0);signal ramoen   : std_logic_vector(4 downto 0);signal rwen     : std_logic_vector(3 downto 0);signal rwenx    : std_logic_vector(3 downto 0);signal romsn    : std_logic_vector(1 downto 0);signal iosn     : std_ulogic;signal oen      : std_ulogic;signal read     : std_ulogic;signal writen   : std_ulogic;signal brdyn    : std_ulogic;signal bexcn    : std_ulogic;signal wdog     : std_ulogic;signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;signal test     : std_ulogic;signal error    : std_logic;signal pio	: std_logic_vector(15 downto 0);signal GND      : std_ulogic := '0';signal VCC      : std_ulogic := '1';signal NC       : std_ulogic := 'Z';signal clk2     : std_ulogic := '1';signal sdcke    : std_logic_vector ( 1 downto 0);  -- clk ensignal sdcsn    : std_logic_vector ( 1 downto 0);  -- chip selsignal sdwen    : std_ulogic;                       -- write ensignal sdrasn   : std_ulogic;                       -- row addr stbsignal sdcasn   : std_ulogic;                       -- col addr stbsignal sddqm    : std_logic_vector ( 3 downto 0);  -- data i/o masksignal sdclk    : std_ulogic;signal plllock    : std_ulogic;signal txd1, rxd1    : std_ulogic;constant lresp : boolean := false;begin-- clock and reset  clk <= not clk after ct * 1 ns;  rst <= '0', '1' after clkperiod*100 * 1 ns;  rxd1 <= '1';  d3 : leon3pci	generic map (ncpu => ncpu, tech => tech, memtype => memtype, pci => pci, disas => disas,		     blength => blength, fifodepth => fifodepth,pcimasteren => pcimasteren,		     pci_dev_id => pci_dev_id, pci_vend_id => pci_vend_id, clkper => clkper,		     memtech => memtech)        port map (rst, clk, clk,  error, address(27 downto 0),	data, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm,	dsutx, dsurx, txd1, rxd1, ramsn, ramoen, rwen, oen, writen,	read, iosn, romsn,	pci_rst, pci_clk, pci_gnt, pci_idsel,	pci_lock, pci_ad, pci_cbe, pci_frame, pci_irdy,	pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,	pci_req, pci_serr, pci_host, pci_66, tbi, tbo);--  ram0: if memtype = 0 generate    prom0 : for i in 0 to 3 generate      sr0 : sram generic map (index => i, abits => 16, fname => promfile)	port map (address(17 downto 2), data(31-i*8 downto 24-i*8), romsn(0),		  rwen(i), oen);    end generate;    sram0 : for i in 0 to 3 generate      sr0 : sram generic map (index => i, abits => 18, fname => sramfile)	port map (address(19 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),		  rwen(i), ramoen(0));    end generate;--  end generate;-- optional sdram  ram1: if memtype = 1 generate      u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)    PORT MAP(              Dq => data(31 downto 16), Addr => address(14 downto 2),              Ba => address(16 downto 15), Clk => clk, Cke => sdcke(0),              Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,              Dqm => sddqm(3 downto 2));      u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)    PORT MAP(              Dq => data(15 downto 0), Addr => address(14 downto 2),              Ba => address(16 downto 15), Clk => clk, Cke => sdcke(0),              Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,              Dqm => sddqm(1 downto 0));      u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)    PORT MAP(              Dq => data(31 downto 16), Addr => address(14 downto 2),              Ba => address(16 downto 15), Clk => clk, Cke => sdcke(0),              Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,              Dqm => sddqm(3 downto 2));      u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)    PORT MAP(              Dq => data(15 downto 0), Addr => address(14 downto 2),              Ba => address(16 downto 15), Clk => clk, Cke => sdcke(0),              Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,              Dqm => sddqm(1 downto 0));  end generate;  error <= 'H';			  -- ERROR pull-up   iuerr : process(error)  begin    assert (error /= '0')      report "*** IU in error mode, test failed! ***"        severity failure ;  end process;  data <= buskeep(data), (others => 'H') after 25 ns;  dsucom : process    procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is    variable w32 : std_logic_vector(31 downto 0);    variable c8  : std_logic_vector(7 downto 0);    constant txp : time := 160 * 1 ns;    begin    dsutx <= '1';    wait for 5000 ns;    txc(dsutx, 16#55#, txp);		-- sync uart    txc(dsutx, 16#80#, txp);    txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);    rxi(dsurx, w32, txp, lresp);    txc(dsutx, 16#a0#, txp);    txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);    rxi(dsurx, w32, txp, lresp);    txc(dsutx, 16#a0#, txp);    txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);    rxi(dsurx, w32, txp, lresp);    txc(dsutx, 16#a0#, txp);    txa(dsutx, 16#80#, 16#00#, 16#00#, 16#00#, txp);    rxi(dsurx, w32, txp, lresp);    end;  begin--  dsucfg(dsutx, dsurx);    wait;  end process;end ;